EPM5032JC-20 vs EPM5064JC Comparison

Detailed side-by-side comparison of EPM5032JC-20 by Altera and EPM5064JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5032JC-20 EPM5064JC
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $7.10
Product Type UV-erasable Programmable Logic Device (PLD) β€”
Family MAX 5000 MAX 5000
Macrocells 32 64
Logic Array Blocks (LABs) 1 β€”
Product Terms (P-terms) 320 β€”
Propagation Delay (tPD) 20 ns β€”
Maximum Clock Frequency 62.5 MHz β€”
Setup Time 10 ns β€”
I/O Lines 16 (bidirectional) β€”
Dedicated Inputs 8 β€”
Total Inputs 24 β€”
Package 68-pin JLCC (windowed ceramic) 68-pin PLCC (JEDEC)
Process Technology CMOS β€”
Erase Method UV (12V VPP + ultraviolet exposure) β€”
Programming Voltage (VPP) 12 V β€”
Architecture PAL-type AND-OR array with PIA interconnect β€”
Lifecycle Status Obsolete (legacy Altera MAX 5000) β€”
Device Type β€” EPLD (Erasable PLD)
Usable Gates β€” 1,250 (approx.)
Logic Array Inputs β€” 36
Logic Array Outputs β€” 64
Mounting Type β€” Surface Mount (socketed)
Supply Voltage (VCC) β€” 5 V (typical, 4.75 V - 5.25 V range)
I/O Logic Level β€” TTL / CMOS compatible
Configuration Memory β€” EPROM (UV-erasable window or OTP)
Operating Temperature β€” [DATA_NEEDED: operating temperature grade]
Pin-to-Pin Delay (tPD) β€” [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) β€” [DATA_NEEDED: fCNT grade value]
RoHS Status β€” [DATA_NEEDED: RoHS compliance]
Lead-Free β€” [DATA_NEEDED: lead-free status]
MSL Level β€” [DATA_NEEDED: MSL rating]
Programming Tool β€” Altera MAX+PLUS II / Quartus II (legacy device support)

Datasheets & Resources

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