EPM5032JC-20 vs EPM5064JC 比較
詳細並排比較 EPM5032JC-20 由 Altera 與 EPM5064JC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032JC-20 | EPM5064JC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | UV-erasable Programmable Logic Device (PLD) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 32 | 64 |
| Logic Array Blocks (LABs) | 1 | — |
| Product Terms (P-terms) | 320 | — |
| Propagation Delay (tPD) | 20 ns | — |
| 最大時脈頻率 | 62.5 MHz | — |
| Setup Time | 10 ns | — |
| I/O Lines | 16 (bidirectional) | — |
| Dedicated Inputs | 8 | — |
| Total Inputs | 24 | — |
| 封裝 | 68-pin JLCC (windowed ceramic) | 68-pin PLCC (JEDEC) |
| Process Technology | CMOS | — |
| Erase Method | UV (12V VPP + ultraviolet exposure) | — |
| Programming Voltage (VPP) | 12 V | — |
| Architecture | PAL-type AND-OR array with PIA interconnect | — |
| 生命週期狀態 | Obsolete (legacy Altera MAX 5000) | — |
| Device Type | — | EPLD (Erasable PLD) |
| Usable Gates | — | 1,250 (approx.) |
| Logic Array Inputs | — | 36 |
| Logic Array Outputs | — | 64 |
| 安裝類型 | — | Surface Mount (socketed) |
| Supply Voltage (VCC) | — | 5 V (typical, 4.75 V - 5.25 V range) |
| I/O Logic Level | — | TTL / CMOS compatible |
| Configuration Memory | — | EPROM (UV-erasable window or OTP) |
| 工作溫度 | — | [DATA_NEEDED: operating temperature grade] |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: specific tPD grade value] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fCNT grade value] |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus II (legacy device support) |