EPM5032LC-15 vs EPM5032PC-15 Comparison
Detailed side-by-side comparison of EPM5032LC-15 by Altera and EPM5032PC-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5032LC-15 | EPM5032PC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $8.20 | $8.10 |
| Family | MAX 5000 EPLD | β |
| Architecture | PAL-type AND/OR with PIA | β |
| Usable Gates | 600 | 600 |
| Macrocells | 32 | β |
| Logic Array Blocks (LABs) | 4 | β |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | 16 |
| Maximum Operating Frequency | 83.3 MHz | β |
| Pin-to-Pin Delay (tPD) | 15 ns | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | β |
| Technology | CMOS EPROM, 1.0 um process | β |
| Programmability | UV-Erasable / OTP | β |
| Package | JLCC-28 (windowed ceramic) | 28-pin PDIP (PC suffix = windowed CerDIP) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS Status | Non-compliant (contains Pb, ceramic-windowed package) | Non-compliant (CerDIP window, contains Be) |
| Device Family | β | MAX 5000 |
| Device Type | β | EPLD (Erasable PLD) |
| Macro Cells | β | 32 |
| Logic Elements / LABs | β | 1 LAB (4 macrocells per group) |
| Propagation Delay (tPD) | β | 15 ns |
| Maximum Internal Frequency | β | 76.9 MHz (some sources list 83.3 MHz) |
| Operating Voltage (VCC) | β | 5 V (typ.) |
| Technology Node | β | 0.8 micron CMOS |
| Configuration Memory | β | UV-Erasable EPROM |
| Total Array Inputs | β | 24 |
| Pin/Package Suffix | β | PC = Windowed Ceramic DIP |
| Speed Grade | β | 15 (15 ns tPD) |
| Programming Tool | β | Altera Logic Programmer + MAX+plus II |
| Lead-Free | β | No |
| Mounting Type | β | Through-Hole (DIP) |