EPM5032LC-15 vs EPM5032PC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032LC-15 sa pamamagitan ng Altera at EPM5032PC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032LC-15 | EPM5032PC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 EPLD | — |
| Architecture | PAL-type AND/OR with PIA | — |
| Usable Gates | 600 | 600 |
| Macrocells | 32 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | 16 |
| Maximum Operating Frequency | 83.3 MHz | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS EPROM, 1.0 um process | — |
| Programmability | UV-Erasable / OTP | — |
| Packhaging | JLCC-28 (windowed ceramic) | 28-pin PDIP (PC suffix = windowed CerDIP) |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Tindminan RoHS | Non-compliant (contains Pb, ceramic-windowed package) | Non-compliant (CerDIP window, contains Be) |
| Device Family | — | MAX 5000 |
| Device Type | — | EPLD (Erasable PLD) |
| Macro Cells | — | 32 |
| Logic Elements / LABs | — | 1 LAB (4 macrocells per group) |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Internal Frequency | — | 76.9 MHz (some sources list 83.3 MHz) |
| Operating Voltage (VCC) | — | 5 V (typ.) |
| Technology Node | — | 0.8 micron CMOS |
| Configuration Memory | — | UV-Erasable EPROM |
| Total Array Inputs | — | 24 |
| Pin/Package Suffix | — | PC = Windowed Ceramic DIP |
| Speed Grade | — | 15 (15 ns tPD) |
| Programming Tool | — | Altera Logic Programmer + MAX+plus II |
| Lead-Free | — | No |
| Uri ng Pagpapasok | — | Through-Hole (DIP) |