EPM5032LC-15 vs EPM5032PC-15 比較
詳細並排比較 EPM5032LC-15 由 Altera 與 EPM5032PC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032LC-15 | EPM5032PC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 EPLD | — |
| Architecture | PAL-type AND/OR with PIA | — |
| Usable Gates | 600 | 600 |
| Macrocells | 32 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | 16 |
| Maximum Operating Frequency | 83.3 MHz | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS EPROM, 1.0 um process | — |
| Programmability | UV-Erasable / OTP | — |
| 封裝 | JLCC-28 (windowed ceramic) | 28-pin PDIP (PC suffix = windowed CerDIP) |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS 狀態 | Non-compliant (contains Pb, ceramic-windowed package) | Non-compliant (CerDIP window, contains Be) |
| Device Family | — | MAX 5000 |
| Device Type | — | EPLD (Erasable PLD) |
| Macro Cells | — | 32 |
| Logic Elements / LABs | — | 1 LAB (4 macrocells per group) |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Internal Frequency | — | 76.9 MHz (some sources list 83.3 MHz) |
| Operating Voltage (VCC) | — | 5 V (typ.) |
| Technology Node | — | 0.8 micron CMOS |
| Configuration Memory | — | UV-Erasable EPROM |
| Total Array Inputs | — | 24 |
| Pin/Package Suffix | — | PC = Windowed Ceramic DIP |
| Speed Grade | — | 15 (15 ns tPD) |
| Programming Tool | — | Altera Logic Programmer + MAX+plus II |
| Lead-Free | — | No |
| 安裝類型 | — | Through-Hole (DIP) |