EPM5032LC-25 vs EPM5032LC-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032LC-25 sa pamamagitan ng Altera at EPM5032LC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5032LC-25 EPM5032LC-20
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Device Family MAX 5000 MAX 5000
Architecture PAL-type EPLD (Erasable Programmable Logic Device) —
Technology CMOS, UV-erasable / OTP —
Macrocells 32 32
Product Terms 320 —
Dedicated Inputs 7 7
I/O Pins 16 bidirectional —
Total Inputs 24 (7 dedicated + 16 I/O used as input) 24
Propagation Delay (tPD) 25 ns 20 ns
Maximum Internal Frequency 62.5 MHz —
Supply Voltage (VCC) 5 V ±10% (4.5 V to 5.5 V) 5 V ±5%
I/O Standard 5 V CMOS —
Temperature na Operasyon 0 °C to +70 °C (commercial, "LC" suffix) 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants)
Packhaging 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch LCC-28 (Plastic Leaded Chip Carrier, J-lead)
Uri ng Pagpapasok Surface Mount, socket-compatible Surface Mount
Configuration Cell Programmable interconnect array (PIA), OTP / UV-erasable —
Tindminan RoHS Not RoHS compliant (legacy Altera product) [DATA_NEEDED: RoHS status]
Product Type — EPLD / CPLD (One-Time Programmable / UV-Erasable)
Usable Gates — 600 gates
Logic Blocks (LABs) — 1
Speed Grade — -20 (20 ns pin-to-pin)
Maximum Frequency — 71.4 MHz
Bidirectional I/O Pins — 16
Output Functions — 16
Product Terms per Output — 16
Programmable Interconnect — Programmable Interconnect Array (PIA)
Level ng MSL — [DATA_NEEDED: MSL]

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