EPM5064JC-1 vs EPM5032JC Comparison

Detailed side-by-side comparison of EPM5064JC-1 by Altera and EPM5032JC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5064JC-1 EPM5032JC
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $18.25 $13.50
Family MAX 5000 MAX 5000 EPLD
Device Type EPLD (Erasable Programmable Logic Device) β€”
Macro Cells 64 β€”
Usable Gates 1250 (typical) β€”
Logic Elements 128 (Logic Array Blocks) β€”
Maximum Operating Frequency 33.3 MHz (fCNT) β€”
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD typical/max in ns] β€”
Supply Voltage (VCC) 5 V nominal (4.75 V – 5.25 V) 5 V
Process Technology 0.8 Β΅m CMOS β€”
Programmable Pins 36 (typical I/O, 44-pin PLCC) β€”
Dedicated Inputs [DATA_NEEDED: dedicated input count] β€”
Package 44-pin PLCC (J-lead, windowed ceramic) PLCC-44
Mounting Type Surface Mount (PLCC socket recommended) Surface Mount (J-lead)
Operating Temperature 0 Β°C to +70 Β°C (commercial, -JC suffix) 0C to +70C (commercial)
Erasure Method UV-erasable through quartz window β€”
Programming Method Altera Logic Programmer + MasterBlaster/ByteBlasterMV β€”
JTAG Boundary Scan Not supported (classic MAX architecture) β€”
RoHS Status Non-compliant (windowed ceramic, contains Pb in glass frit) unknown
Military/Avionics SMD 5962-01-417-3750 (QML variant: EPM5064JM/883) β€”
Macrocells β€” 32
Logic Gates β€” 600 usable gates
Maximum I/O Pins β€” 40
Propagation Delay (tPD) β€” [DATA_NEEDED: specific speed grade value]
Input Type β€” TTL-compatible
Output Type β€” TTL/CMOS-compatible
Programmability β€” UV-erasable (windowed ceramic) / OTP variants
Design Software β€” MAX+PLUS II / Quartus legacy
JEDEC Standard β€” JEDEC PLCC-44 footprint
Lead-Free β€” unknown

Datasheets & Resources

Browse All Products Create BOM Request Quote