EPM5064JC-1 vs EPM5032JC Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5064JC-1 sa pamamagitan ng Altera at EPM5032JC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5064JC-1 EPM5032JC
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 5000 MAX 5000 EPLD
Device Type EPLD (Erasable Programmable Logic Device) —
Macro Cells 64 —
Usable Gates 1250 (typical) —
Logic Elements 128 (Logic Array Blocks) —
Maximum Operating Frequency 33.3 MHz (fCNT) —
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD typical/max in ns] —
Supply Voltage (VCC) 5 V nominal (4.75 V – 5.25 V) 5 V
Process Technology 0.8 µm CMOS —
Programmable Pins 36 (typical I/O, 44-pin PLCC) —
Dedicated Inputs [DATA_NEEDED: dedicated input count] —
Packhaging 44-pin PLCC (J-lead, windowed ceramic) PLCC-44
Uri ng Pagpapasok Surface Mount (PLCC socket recommended) Surface Mount (J-lead)
Temperature na Operasyon 0 °C to +70 °C (commercial, -JC suffix) 0C to +70C (commercial)
Erasure Method UV-erasable through quartz window —
Programming Method Altera Logic Programmer + MasterBlaster/ByteBlasterMV —
JTAG Boundary Scan Not supported (classic MAX architecture) —
Tindminan RoHS Non-compliant (windowed ceramic, contains Pb in glass frit) unknown
Military/Avionics SMD 5962-01-417-3750 (QML variant: EPM5064JM/883) —
Macrocells — 32
Logic Gates — 600 usable gates
Maximum I/O Pins — 40
Propagation Delay (tPD) — [DATA_NEEDED: specific speed grade value]
Input Type — TTL-compatible
Type ng Output — TTL/CMOS-compatible
Programmability — UV-erasable (windowed ceramic) / OTP variants
Design Software — MAX+PLUS II / Quartus legacy
JEDEC Standard — JEDEC PLCC-44 footprint
Lead-Free — unknown

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