EPM5064JC-1 vs EPM5032JC 比較
詳細並排比較 EPM5064JC-1 由 Altera 與 EPM5032JC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5064JC-1 | EPM5032JC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macro Cells | 64 | — |
| Usable Gates | 1250 (typical) | — |
| Logic Elements | 128 (Logic Array Blocks) | — |
| Maximum Operating Frequency | 33.3 MHz (fCNT) | — |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: tPD typical/max in ns] | — |
| Supply Voltage (VCC) | 5 V nominal (4.75 V – 5.25 V) | 5 V |
| Process Technology | 0.8 µm CMOS | — |
| Programmable Pins | 36 (typical I/O, 44-pin PLCC) | — |
| Dedicated Inputs | [DATA_NEEDED: dedicated input count] | — |
| 封裝 | 44-pin PLCC (J-lead, windowed ceramic) | PLCC-44 |
| 安裝類型 | Surface Mount (PLCC socket recommended) | Surface Mount (J-lead) |
| 工作溫度 | 0 °C to +70 °C (commercial, -JC suffix) | 0C to +70C (commercial) |
| Erasure Method | UV-erasable through quartz window | — |
| Programming Method | Altera Logic Programmer + MasterBlaster/ByteBlasterMV | — |
| JTAG Boundary Scan | Not supported (classic MAX architecture) | — |
| RoHS 狀態 | Non-compliant (windowed ceramic, contains Pb in glass frit) | unknown |
| Military/Avionics SMD | 5962-01-417-3750 (QML variant: EPM5064JM/883) | — |
| Macrocells | — | 32 |
| Logic Gates | — | 600 usable gates |
| Maximum I/O Pins | — | 40 |
| Propagation Delay (tPD) | — | [DATA_NEEDED: specific speed grade value] |
| Input Type | — | TTL-compatible |
| 輸出類型 | — | TTL/CMOS-compatible |
| Programmability | — | UV-erasable (windowed ceramic) / OTP variants |
| Design Software | — | MAX+PLUS II / Quartus legacy |
| JEDEC Standard | — | JEDEC PLCC-44 footprint |
| Lead-Free | — | unknown |