EPM5128GC - 128-Macrocell MAX 5000 CPLD | Altera | 68-Pin PGA
MPN: EPM5128GC β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $27.4 | $2,740.00 |
| 500 | $22.95 | $11,475.00 |
| 1,000 | $19.2 | $19,200.00 |
Drop-in alternatives for EPM5128GC β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM5128GC-1
β Drop-Inβ In Stock
$18.95 / Unit
View Datasheet βEPM5064JC-1
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$18.25 / Unit
View Datasheet βEPM5064JC
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$7.1 / Unit
View Datasheet βEPM5064JC-2
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$23.1 / Unit
View Datasheet βEPM5032DC-2
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$8.75 / Unit
View Datasheet βEPM5128GC Maximum Ratings & Electrical Characteristics
| Family | MAX 5000 |
| Macrocells | 128 |
| Usable Gates | 2,500 |
| User I/Os | 68 |
| Package Type | WPGA (Windowed Ceramic Pin Grid Array) |
| Package Code | WPGA |
| Number of Terminals | 68 |
| Terminal Form | PIN/PEG (through-hole PGA with alignment pegs) |
| Package Shape | Square |
| Temperature Grade | Commercial |
| Supply Voltage (Vcc) | 5 V |
| Process Technology | CMOS, UV-erasable |
| Architecture | EPLD, programmable AND/OR array with fixed OR plane |
| Programmable Security Bit | Yes |
| Configuration Memory | Non-volatile UV-EPROM (windowed ceramic) |
| Mounting Type | Through-Hole (PGA socket required) |
EPM5128GC Pin Configuration
| Pin 1 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 2 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 3 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 4 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 5 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 6 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 7 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 8 | GND β Ground |
| Pin 9 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 10 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 11 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 12 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 13 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 14 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 15 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 16 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 17 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 18 | VCC β 5V supply |
| Pin 19 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 20 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 21 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 22 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 23 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 24 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 25 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 26 | GND β Ground |
| Pin 27 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 28 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 29 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 30 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 31 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 32 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 33 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 34 | VCC β 5V supply |
| Pin 35 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 36 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 37 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 38 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 39 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 40 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 41 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 42 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 43 | GND β Ground |
| Pin 44 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 45 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 46 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 47 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 48 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 49 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 50 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 51 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 52 | VCC β 5V supply |
| Pin 53 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 54 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 55 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 56 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 57 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 58 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 59 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 60 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 63 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 64 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 65 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 66 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 67 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
| Pin 68 | I/O β User I/O pin (assigned by MAX+PLUS II design) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5128GC is suitable for 6 applications: Legacy Glue-Logic Consolidation, Address Decoding and Bus Bridging, UV-Erasable Design Prototyping, Industrial Control State Machines, Peripheral Interface Bridging, Avionics and Military Legacy Maintenance.
Legacy Glue-Logic Consolidation
The EPM5128GC consolidates dozens of discrete 74-series TTL and CMOS glue-logic gates into a single 128-macrocell EPLD, simplifying PCB layout and improving noise immunity in long-life industrial control systems. With 68 user I/Os and predictable MAX 5000 propagation delays, the part directly replaces multiple PAL/GAL devices in backplane interface cards where deterministic timing matters more than raw throughput. Designers port legacy AHDL/VHDL code from MAX+PLUS II and program the device via JTAG.
Recommended
Address Decoding and Bus Bridging
The EPM5128GC is well suited to multi-channel address decoding on legacy ISA, VME, and proprietary backplane buses, where 128 macrocells can decode several megabytes of address space with sub-nanosecond deterministic delay. Its 5V-tolerant I/Os interface directly with TTL bus transceivers without level shifters, simplifying the BOM. The non-volatile UV-EPROM configuration eliminates boot PROM requirements, an advantage over SRAM-based FPGAs in mission-critical industrial systems.
Recommended
UV-Erasable Design Prototyping
The ceramic windowed PGA (WPGA) package is the EPM5128GC's defining feature for prototyping: the quartz window exposes the EPROM array to UV light, allowing the entire 128-macrocell logic pattern to be erased and re-programmed dozens of times during iterative design cycles. This is invaluable in university and engineering-lab environments where iterative verification requires frequent bitstream updates. Production units migrate to one-time-programmable plastic packages for volume deployment.
Recommended
Industrial Control State Machines
Factory automation controllers using the EPM5128GC implement complex Mealy and Moore state machines that coordinate conveyor sequencing, robotic arm interlocks, and safety watchdog logic with deterministic sub-25ns propagation delays. The 5V I/O directly drives industrial 24V opto-isolated inputs via resistor networks, while the wide commercial temperature grade covers most factory floor environments. For harsher conditions, designers migrate to MAX II/MAX V industrial-grade equivalents.
Recommended
Peripheral Interface Bridging
The EPM5128GC bridges legacy parallel ports, SCSI interfaces, and custom peripheral buses to modern microcontrollers by implementing bus-format converters, FIFO controllers, and DMA handshaking state machines in a single chip. With 68 user I/Os, the device handles 16-bit data buses plus full handshaking without external mux/demux logic. The MAX architecture's fixed interconnect guarantees predictable timing across voltage and temperature corners, simplifying timing closure.
Recommended
Avionics and Military Legacy Maintenance
Avionics and military platforms fielded in the 1990s used the EPM5128GC for mission-computer interface logic, and many of those platforms remain in service decades later, requiring authentic replacement parts for scheduled maintenance. The ceramic WPGA package and -55C to +125C military screening variants (EPM5128GM/883B family) make the part uniquely suited to these long-life programs. Distributors specializing in obsolete military components maintain traceable stock for these applications.
Recommended
Recommended Products Summary
Engineering reference data for EPM5128GC β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5128GC-1 | EPM5064JC-1 | EPM5064JC | EPM5064JC-2 | EPM5032DC-2 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | WPGA-68 (Windowed Ceramic PGA) | WPGA-68 (Windowed Ceramic PGA) - same | WPGA-68 (Windowed Ceramic PGA) - same | WPGA-68 (Windowed Ceramic PGA) - same | WPGA-68 (Windowed Ceramic PGA) - same | WPGA-68 (Windowed Ceramic PGA) - same |
| Macrocells | 128 | 128 (same) | 64 (-50%) | 64 (-50%) | 64 (-50%) | 32 (-75%) |
| Usable Gates | 2,500 | 2,500 | 2,000 | 2,000 | 2,000 | 1,000 |
| User I/Os | 68 | 68 | 68 | 68 | 68 | 68 (lower drive strength) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Speed/Power Grade | Standard | -1 grade (higher speed option) | -1 grade | Standard | -2 grade | -2 grade |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Erasure Method | UV (windowed) | UV (windowed) | UV (windowed) | UV (windowed) | UV (windowed) | UV (windowed) |
Key Differentiators
- Highest-density MAX 5000 device with 128 macrocells (vs EPM5064JC)
- Same WPGA-68 footprint with higher gate count (vs EPM5032DC-2)
- Windowed UV-erasable package for iterative prototyping (vs MAX II EPM240T100C5N (TQFP-100))
Design Notes
The EPM5128GC uses a 68-pin ceramic Pin Grid Array (PGA) package that requires a through-hole PGA socket for programming and UV erasure cycles. When laying out the PCB, reserve a socket footprint with adequate clearance around the ceramic body so the UV eraser lamp can reach the quartz window without obstruction. For production runs, migrate to a one-time-programmable (OTP) plastic package such as the MAX 5000 equivalent in PDIP or PLCC to eliminate the socket cost.
Provide a clean 5V supply to the EPM5128GC with a 100nF ceramic bypass capacitor within 5mm of each VCC pin (multiple VCC and GND pins are distributed across the PGA). Add a 10uF tantalum bulk capacitor at the board entry point. The MAX 5000 family draws substantial inrush current during programming; ensure your 5V regulator can source the Icc peak without sagging, which could corrupt the JTAG programming sequence.
Do not rely on the EPM5128GC for new designs; the MAX 5000 family was discontinued by Altera (now Intel) and the part is in obsolescence with limited inventory. For new development, select a MAX II (EPM240T100C5N), MAX V, or MAX 10 CPLD/FPGA which provide more macrocells, surface-mount packaging, lower power, and active toolchain support. EPM5128GC should be reserved for maintenance of legacy equipment originally designed around it.
When interfacing the EPM5128GC with TTL buses at high edge rates, place 33 ohm series damping resistors on outputs that drive more than 4 inches of trace or fan out to multiple loads, to suppress transmission-line ringing. Use a ground plane on layer 2 of the PCB and keep all I/O traces short (< 2 inches where possible) to control crosstalk. The MAX architecture's deterministic timing assumes lumped-load conditions, so loading analysis is part of the timing closure.
Compliance Information
Compliance status not confirmed in available datasheets; the EPM5128GC is an obsolete part from the 1990s and predates modern RoHS documentation requirements. The ceramic PGA package historically contains lead-bearing solder, so RoHS compliance is unlikely; verify with the actual part supplier before using in RoHS-restricted designs.
