EPM5128JC-1 vs EPM5128GC Comparison
Detailed side-by-side comparison of EPM5128JC-1 by Altera and EPM5128GC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5128JC-1 | EPM5128GC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Erasable Programmable Logic Device (EPLD/CPLD) | — |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 40 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Package | 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) | — |
| Mounting Type | Surface Mount | Through-Hole (PGA socket required) |
| Operating Temperature | [DATA_NEEDED: temperature grade] | — |
| Programming Interface | JTAG / Altera dedicated programmer | — |
| Configuration Memory | Non-volatile EPROM (UV-erasable) | Non-volatile UV-EPROM (windowed ceramic) |
| RoHS Status | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS compliance] |
| Lifecycle Status | Obsolete - last-time-buy inventory only | — |
| Logic Elements / LABs | — | [DATA_NEEDED: LAB count] |
| User I/Os | — | 68 |
| Package Type | — | WPGA (Windowed Ceramic Pin Grid Array) |
| Package Code | — | WPGA |
| Number of Terminals | — | 68 |
| Terminal Form | — | PIN/PEG (through-hole PGA with alignment pegs) |
| Package Shape | — | Square |
| Temperature Grade | — | Commercial |
| Supply Voltage (Vcc) | — | 5 V |
| Process Technology | — | CMOS, UV-erasable |
| Architecture | — | EPLD, programmable AND/OR array with fixed OR plane |
| Propagation Delay (tpd) | — | [DATA_NEEDED: tpd in ns] |
| Maximum Frequency (fmax) | — | [DATA_NEEDED: fmax in MHz] |
| Programmable Security Bit | — | Yes |