EPM5128JC-1 vs EPM5128GC 对比

详细并排对比 EPM5128JC-1 出自 Altera 和 EPM5128GC 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5128JC-1 EPM5128GC
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $24.95 $19.20
Family MAX 5000 MAX 5000
Device Type Erasable Programmable Logic Device (EPLD/CPLD) —
Macrocells 128 128
Usable Gates 2,500 2,500
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] —
Maximum Operating Frequency 62.5 MHz —
Pin-to-Pin Propagation Delay (tPD) 40 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Technology CMOS, UV-erasable EPROM —
封装 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) —
安装类型 Surface Mount Through-Hole (PGA socket required)
工作温度 [DATA_NEEDED: temperature grade] —
Programming Interface JTAG / Altera dedicated programmer —
Configuration Memory Non-volatile EPROM (UV-erasable) Non-volatile UV-EPROM (windowed ceramic)
RoHS 状态 non_compliant (ceramic windowed package) [DATA_NEEDED: RoHS compliance]
生命周期状态 Obsolete - last-time-buy inventory only —
Logic Elements / LABs — [DATA_NEEDED: LAB count]
User I/Os — 68
Package Type — WPGA (Windowed Ceramic Pin Grid Array)
Package Code — WPGA
Number of Terminals — 68
Terminal Form — PIN/PEG (through-hole PGA with alignment pegs)
Package Shape — Square
Temperature Grade — Commercial
Supply Voltage (Vcc) — 5 V
Process Technology — CMOS, UV-erasable
Architecture — EPLD, programmable AND/OR array with fixed OR plane
Propagation Delay (tpd) — [DATA_NEEDED: tpd in ns]
Maximum Frequency (fmax) — [DATA_NEEDED: fmax in MHz]
Programmable Security Bit — Yes

数据手册与资源

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