EPM5128JC vs EPM5128LC-1 Comparison
Detailed side-by-side comparison of EPM5128JC by Altera and EPM5128LC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5128LC-1
EPM5128LC-1 - 128-Macrocell MAX 5000 CPLD | Altera | 5V 68-Pin PLCC
EPM5128LC-1 ObsoleteSpecification Comparison
| Parameter | EPM5128JC | EPM5128LC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $8.20 |
| Product Family | MAX 5000 | β |
| Device Type | EPLD / CPLD | β |
| Macrocell Count | 128 | β |
| Propagation Delay (tPD) | 35 ns | β |
| Logic Elements | Programmable AND/OR/XOR array | β |
| Supply Voltage (VCC) | 5 V (typical) | 5 V (Β±10%) |
| Number of Pins | 68 | β |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded | 68-pin J-lead ceramic chip carrier (PLCC windowed) |
| Dedicated Inputs | 8 | 7 |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | β |
| Configuration Memory | UV-erasable EPROM (windowed package) | β |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer | β |
| Operating Temperature | Commercial 0C to +70C | 0C to +70C (commercial) |
| Mounting Type | Surface Mount (PLCC socket or solder) | Surface Mount (J-lead PLCC socket compatible) |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) | β |
| Process Technology | CMOS EPROM | CMOS EPROM, UV-erasable |
| RoHS Status | [DATA_NEEDED: RoHS status - legacy part] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Family | β | MAX 5000 |
| Logic Elements / Macrocells | β | 128 macrocells |
| Number of Usable Gates | β | [DATA_NEEDED: usable gates] |
| Bidirectional I/O Pins | β | 52 |
| Total User I/O | β | 60 (max) |
| Propagation Delay (tpd) | β | 30 ns |
| Programmability | β | UV-erasable / OTP (windowed package) |
| JTAG Support | β | IEEE 1149.1 boundary-scan |