EPM5128JC - 128-Macrocell MAX 5000 CPLD, 35ns, PLCC-68 | Altera
MPN: EPM5128JC ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
Drop-in alternatives for EPM5128JC — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM5128JC-1
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View Datasheet →EPM5128GM883B
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View Datasheet →EPM5128GM/883B
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View Datasheet →EPM5128GI
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View Datasheet →EPM5128GC-1
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View Datasheet →EPM5128GC-2
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View Datasheet →EPM5128JC Maximum Ratings & Electrical Characteristics
| Product Family | MAX 5000 |
| Device Type | EPLD / CPLD |
| Macrocell Count | 128 |
| Propagation Delay (tPD) | 35 ns |
| Logic Elements | Programmable AND/OR/XOR array |
| Supply Voltage (VCC) | 5 V (typical) |
| Number of Pins | 68 |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded |
| Dedicated Inputs | 8 |
| Configuration Memory | UV-erasable EPROM (windowed package) |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Operating Temperature | Commercial 0C to +70C |
| Mounting Type | Surface Mount (PLCC socket or solder) |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) |
| Process Technology | CMOS EPROM |
EPM5128JC plcc-68 (jlcc) ceramic, j-leaded Pin Configuration Guide
Complete pinout information for EPM5128JC (plcc-68 (jlcc) ceramic, j-leaded package) with [DATA_NEEDED: user I/O pin count] pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM5128JC.
Refer to the datasheet for full pin configuration.
Estimated pin count: [DATA_NEEDED: user I/O pin count] pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5128JC is suitable for 7 applications: Legacy 5 V ISA / VME Bus Glue Logic, Industrial PLC State-Machine Controllers, Vintage Printer and Disk-Controller Glue, 8/16-bit Microprocessor Address Decoding, Telecom Backplane Interface Logic, Pin-Compatible TTL Replacement, Avionics Legacy Retrofit Programs.
Legacy 5 V ISA / VME Bus Glue Logic
The EPM5128JC's 128 macrocells, 5 V single-supply operation, and 35 ns deterministic propagation delay make it ideal for consolidating address decoding, bus arbitration, and wait-state generation in legacy ISA, VME, and STD bus systems. Its ceramic PLCC-68 windowed package supports iterative UV-erase-reprogram cycles during board bring-up, while its AND/OR array architecture absorbs 6-10 TTL/MSI packages per device, reducing board area and improving noise margin on long backplane traces.
Recommended
Industrial PLC State-Machine Controllers
For industrial PLC scan-engine and ladder-logic-emulation designs, the EPM5128JC provides the macrocell count and registered-logic density required to implement multi-state sequencers, PWM generators, and encoder counters in a single device. Its predictable 35 ns pin-to-pin timing ensures deterministic response under all temperature and loading conditions, critical for safety-relevant control loops. The wide commercial operating range and ceramic-package reliability suit factory-floor environments with extended thermal stress and vibration.
Recommended
Vintage Printer and Disk-Controller Glue
Legacy parallel-port printers, SCSI disk controllers, and Centronics-interface peripherals used the EPM5128JC to consolidate 30-50 discrete 74LS TTL packages into a single programmable device, shrinking PCB real-estate and improving timing margin on parallel data buses. Its bidirectional I/O architecture simplifies data-bus transceiver control, and its non-volatile UV-erasable configuration memory retained logic across power cycles without external boot devices - a key advantage in pre-flash-CPLD designs.
Recommended
8/16-bit Microprocessor Address Decoding
The EPM5128JC was widely used to replace discrete 74LS138 / 74LS139 decoder trees in 8086, 68000, Z80, and 8051-family microprocessor designs, providing full 64 KB or 1 MB address-space decoding with chip-select outputs in a single device. Its 128 macrocells support 8-16 independent chip-select regions plus wait-state and bus-acknowledge logic, and its 35 ns propagation delay fits within one clock cycle of most 8-25 MHz microprocessors of the era, eliminating external wait-state generation.
Recommended
Telecom Backplane Interface Logic
In telecom T1/E1 and early-SDH backplane designs, the EPM5128JC implemented multi-channel framing, alarm-collection, and line-interface control logic where its 128 macrocells mapped cleanly onto 4-8 independent state machines per device. The ceramic PLCC-68 package provided the long-term reliability demanded by central-office equipment, and the 5 V supply matched the bipolar ECL/TTL interface voltages common in telecom backplanes of that era.
Recommended
Pin-Compatible TTL Replacement
Designers used the EPM5128JC to consolidate random-logic TTL boards containing 30-60 discrete 74LS/74F/74ALS gates, latches, and flip-flops into a single reprogrammable device, often achieving 4:1 or better board-area reduction. The deterministic timing and 35 ns delay match discrete-TTL propagation times closely enough that re-routing is unnecessary, and the UV-erasable windowed package enables in-house design changes without re-spinning the PCB - a major cost advantage in long-lifecycle industrial and aerospace programs.
Recommended
Avionics Legacy Retrofit Programs
Avionics retrofit programs on platforms originally certified with MAX 5000-series CPLDs depend on the EPM5128JC as the only form-fit-function replacement for end-of-life support, because re-designing around a modern CPLD would require costly re-certification. The ceramic PLCC-68 package with MIL-PRF-38535 screening variants (EPM5128GM883B) provides the reliability pedigree required for DO-254 DAL-C and DAL-D applications, and the deterministic timing simplifies timing-margin analysis during certification audits.
Recommended
Recommended Products Summary
Engineering reference data for EPM5128JC — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5128JC-1 | EPM5128GM883B | EPM5128GI | EPM5128GC-1 | EPM5128GC-2 |
|---|---|---|---|---|---|---|
| Package | PLCC-68 (ceramic, JLCC, windowed) | PLCC-68 (ceramic, JLCC, windowed) - same | PLCC-68 (ceramic, 883B) - same | PLCC-68 (ceramic, industrial) - same | PLCC-68 (ceramic) - same | PLCC-68 (ceramic) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocell Count | 128 | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 35 ns | ~25-30 ns (faster grade) | 35 ns (military) | 35 ns (industrial) | ~30 ns (commercial -1 grade) | 45 ns (slower grade) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| Temperature Grade | Commercial 0C to +70C | Commercial 0C to +70C | Military -55C to +125C (MIL-PRF-38535) | Industrial -40C to +85C | Commercial 0C to +70C | Commercial 0C to +70C |
| Configuration Memory | UV-erasable EPROM (windowed) | UV-erasable EPROM (windowed) | UV-erasable EPROM (windowed) | UV-erasable EPROM (windowed) | UV-erasable EPROM (windowed) | UV-erasable EPROM (windowed) |
| Lifecycle Status | Obsolete (as of 2026) | Obsolete | Obsolete (military stock only) | Obsolete | Obsolete | Obsolete |
| Approx. 100-piece Price (2026) | $13.85 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Faster speed grade at the same price point (vs EPM5128JC-1)
- Military temperature range available in same package (vs EPM5128GM883B)
- Industrial temperature grade for factory-floor use (vs EPM5128GI)
Design Notes
Estimated: The EPM5128JC operates from a single 5 V +/- 10% supply. At maximum macrocell toggle rate (all 128 FFs at 50 MHz with 50% toggle), ICC draw can reach 200-300 mA. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of each VCC pin and a single 10 uF tantalum bulk capacitor near the package. Add a ferrite bead in series with VCC if the supply shares a rail with switching converters, because EPROM-cell programming-mode voltage transients can cause functional upsets.
PLCC-68 sockets are highly recommended for prototype and field-replaceable applications because the ceramic JLCC package is not designed for repeated hand-soldering. Use a gold-plated machine-pin socket (e.g., AMP 1-822066-6 or 3M 8680-6000) to ensure reliable contact after 100+ insertion cycles. For production, consider wave-soldering with a PLCC-68 footprint with thermal-relief pads and a solder-paste stencil optimized for 0.4 mm pitch leads.
The EPM5128JC uses a UV-erasable EPROM cell that requires 20-30 minutes of exposure to 12 mW/cm^2 UV light (254 nm wavelength) before reprogramming. Cover the window with opaque label during operation, because ambient UV (fluorescent lamps, direct sunlight) can erase configuration over weeks. Also note that unlike flash-based CPLDs, the MAX 5000 family cannot be reprogrammed in-circuit; you must remove the device or use a windowed package on a programmer.
Estimated: At 5 V VCC, 200 mA ICC, and ambient 70C commercial-max, the EPM5128JC ceramic PLCC-68 has a theta_JA of approximately 35-45 C/W, yielding a junction-to-ambient rise of 7-9 C above ambient. The device does not require a heatsink in normal operation, but airflow of 100 LFM is recommended in enclosed industrial enclosures to keep junction temperature below 125C. The military-grade EPM5128GM883B operates at -55C to +125C and has tighter thermal characterization.
Compliance Information
RoHS/REACH/lead-free status not specified in the verified web data; legacy Altera MAX 5000 family (pre-2000s) was typically supplied in non-RoHS ceramic packages. AEC-Q100 is not applicable because this is a programmable logic IC for industrial/avionics rather than automotive-grade silicon.
