EPM5128JC vs EPM5128LC-1 Pengandingan
Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5128JC disebabkan oleh Altera dan EPM5128LC-1 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.
Pengandingan Spesifikasi
| Parametr | EPM5128JC | EPM5128LC-1 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Product Family | MAX 5000 | — |
| Device Type | EPLD / CPLD | — |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Logic Elements | Programmable AND/OR/XOR array | — |
| Supply Voltage (VCC) | 5 V (typical) | 5 V (±10%) |
| Bilangan Pin | 68 | — |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded | 68-pin J-lead ceramic chip carrier (PLCC windowed) |
| Dedicated Inputs | 8 | 7 |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Configuration Memory | UV-erasable EPROM (windowed package) | — |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer | — |
| Suhu Operasi | Commercial 0C to +70C | 0C to +70C (commercial) |
| Jenis Pemasangan | Surface Mount (PLCC socket or solder) | Surface Mount (J-lead PLCC socket compatible) |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) | — |
| Process Technology | CMOS EPROM | CMOS EPROM, UV-erasable |
| Status RoHS | [DATA_NEEDED: RoHS status - legacy part] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Family | — | MAX 5000 |
| Logic Elements / Macrocells | — | 128 macrocells |
| Number of Usable Gates | — | [DATA_NEEDED: usable gates] |
| Bidirectional I/O Pins | — | 52 |
| Total User I/O | — | 60 (max) |
| Propagation Delay (tpd) | — | 30 ns |
| Programmability | — | UV-erasable / OTP (windowed package) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |