EPM5130GI vs EPM5130JI Comparison
Detailed side-by-side comparison of EPM5130GI by Altera and EPM5130JI by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5130GI | EPM5130JI |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $16.20 | $9.75 |
| Device Family | MAX 5000 | β |
| Architecture | EPLD (Erasable Programmable Logic Device), UV-erasable | β |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA) |
| Dedicated Inputs | 19 | β |
| Total Inputs | 68 | β |
| I/O Pins | 48 | β |
| Propagation Delay (tPD) | 55 ns | 55 ns |
| Maximum Clock Frequency (fMAX) | 33.3 MHz | β |
| External Clock Pins | 1 | β |
| Process Technology | CMOS | 0.75 micron CMOS EPROM |
| Supply Voltage | 5 V | 5 V (typical) |
| Package | Ceramic Pin Grid Array (PGA), windowed | β |
| Operating Temperature | -40C to +85C (industrial) | Commercial (0C to +70C) |
| RoHS Status | [DATA_NEEDED: RoHS status] | Non-compliant (contains Pb in ceramic package) |
| Programming Method | UV erasure + EPROM programming | β |
| Family | β | MAX 5000 |
| Device Type | β | UV-Erasable EPLD (CMOS EPROM) |
| Maximum Clock Frequency | β | 33.3 MHz |
| External Clock Inputs | β | 1 (shared input/clock) |
| Input Logic Standard | β | TTL-compatible |
| Package Type | β | Ceramic J-Leaded Chip Carrier (JLCC) with UV window |
| Program/Erase Method | β | UV erasure through quartz window |
| Lifecycle | β | Obsolete - EOL by Altera/Intel |