EPM5130GI vs EPM5130JI Vergleich
Detaillierter Direktvergleich von EPM5130GI von Altera und EPM5130JI von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5130GI | EPM5130JI |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $16,20 | $9,75 |
| Device Family | MAX 5000 | — |
| Architecture | EPLD (Erasable Programmable Logic Device), UV-erasable | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA) |
| Dedicated Inputs | 19 | — |
| Total Inputs | 68 | — |
| I/O Pins | 48 | — |
| Propagation Delay (tPD) | 55 ns | 55 ns |
| Maximum Clock Frequency (fMAX) | 33.3 MHz | — |
| External Clock Pins | 1 | — |
| Process Technology | CMOS | 0.75 micron CMOS EPROM |
| Versorgungsspannung | 5 V | 5 V (typical) |
| Gehäuse | Ceramic Pin Grid Array (PGA), windowed | — |
| Betriebstemperatur | -40C to +85C (industrial) | Commercial (0C to +70C) |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Non-compliant (contains Pb in ceramic package) |
| Programming Method | UV erasure + EPROM programming | — |
| Family | — | MAX 5000 |
| Device Type | — | UV-Erasable EPLD (CMOS EPROM) |
| Maximale Taktfrequenz | — | 33.3 MHz |
| External Clock Inputs | — | 1 (shared input/clock) |
| Input Logic Standard | — | TTL-compatible |
| Package Type | — | Ceramic J-Leaded Chip Carrier (JLCC) with UV window |
| Program/Erase Method | — | UV erasure through quartz window |
| Lifecycle | — | Obsolete - EOL by Altera/Intel |