EPM5130GI vs EPM5130JI Comparación
Comparación detallada lado a lado de EPM5130GI por Altera y EPM5130JI por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5130GI | EPM5130JI |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $16,20 | $9,75 |
| Device Family | MAX 5000 | — |
| Architecture | EPLD (Erasable Programmable Logic Device), UV-erasable | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA) |
| Dedicated Inputs | 19 | — |
| Total Inputs | 68 | — |
| I/O Pins | 48 | — |
| Propagation Delay (tPD) | 55 ns | 55 ns |
| Maximum Clock Frequency (fMAX) | 33.3 MHz | — |
| External Clock Pins | 1 | — |
| Process Technology | CMOS | 0.75 micron CMOS EPROM |
| Tensión de alimentación | 5 V | 5 V (typical) |
| Encapsulado | Ceramic Pin Grid Array (PGA), windowed | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | Commercial (0C to +70C) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (contains Pb in ceramic package) |
| Programming Method | UV erasure + EPROM programming | — |
| Family | — | MAX 5000 |
| Device Type | — | UV-Erasable EPLD (CMOS EPROM) |
| Frecuencia de reloj máxima | — | 33.3 MHz |
| External Clock Inputs | — | 1 (shared input/clock) |
| Input Logic Standard | — | TTL-compatible |
| Package Type | — | Ceramic J-Leaded Chip Carrier (JLCC) with UV window |
| Program/Erase Method | — | UV erasure through quartz window |
| Lifecycle | — | Obsolete - EOL by Altera/Intel |