EPM5130JC-1 vs EPM5128JC-1 Comparison
Detailed side-by-side comparison of EPM5130JC-1 by Altera and EPM5128JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5130JC-1 | EPM5128JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Usable Gates | 2,500 gates | 2,500 |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | [DATA_NEEDED: LAB count] |
| Maximum Operating Frequency | 62.5 MHz | 62.5 MHz |
| Propagation Delay (tPD) | 40 ns | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Dedicated Inputs | 19 | — |
| I/O Pins | 80 | — |
| Package | 84-pin PLCC (J-lead) | 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Technology | UV-erasable EPROM (quartz window) | — |
| Process Technology | CMOS | — |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade] |
| External Clock Pins | 1 global clock | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | non_compliant (ceramic windowed package) |
| Device Type | — | Erasable Programmable Logic Device (EPLD/CPLD) |
| Pin-to-Pin Propagation Delay (tPD) | — | 40 ns |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Interface | — | JTAG / Altera dedicated programmer |
| Configuration Memory | — | Non-volatile EPROM (UV-erasable) |
| Lifecycle Status | — | Obsolete - last-time-buy inventory only |