EPM5130JC-1 vs EPM5128JC-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5130JC-1 sa pamamagitan ng Altera at EPM5128JC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5130JC-1 | EPM5128JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Usable Gates | 2,500 gates | 2,500 |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | [DATA_NEEDED: LAB count] |
| Maximum Operating Frequency | 62.5 MHz | 62.5 MHz |
| Propagation Delay (tPD) | 40 ns | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5 V nominal) |
| Dedicated Inputs | 19 | — |
| I/O Pins | 80 | — |
| Packhaging | 84-pin PLCC (J-lead) | 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programming Technology | UV-erasable EPROM (quartz window) | — |
| Process Technology | CMOS | — |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade] |
| External Clock Pins | 1 global clock | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | non_compliant (ceramic windowed package) |
| Device Type | — | Erasable Programmable Logic Device (EPLD/CPLD) |
| Pin-to-Pin Propagation Delay (tPD) | — | 40 ns |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Interface | — | JTAG / Altera dedicated programmer |
| Configuration Memory | — | Non-volatile EPROM (UV-erasable) |
| Katayuan ng Lifecycle | — | Obsolete - last-time-buy inventory only |