EPM5130WC-2 vs EPM5130JC-1 Comparison
Detailed side-by-side comparison of EPM5130WC-2 by Altera and EPM5130JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5130WC-2 | EPM5130JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-Erasable PLD (CPLD) | CPLD (Complex Programmable Logic Device) |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 45 ns | 40 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| Operating Temperature | 0 °C to 70 °C (Commercial) | 0C to +70C (commercial) |
| Process Technology | CMOS | CMOS |
| Dedicated Inputs | 19 | 19 |
| User I/O Lines | 48 | — |
| Total Inputs (I/O + dedicated) | 68 | — |
| Package Type | 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing | — |
| Terminal Pitch | 0.650 mm | — |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | UV-erasable CMOS EEPROM cells | — |
| Speed Grade | -2 (45 ns) | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements | AND/OR array with programmable macrocell register | — |
| Family | — | MAX 5000 |
| Usable Gates | — | 2,500 gates |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| Maximum Operating Frequency | — | 62.5 MHz |
| I/O Pins | — | 80 |
| Package | — | 84-pin PLCC (J-lead) |
| Programming Technology | — | UV-erasable EPROM (quartz window) |
| External Clock Pins | — | 1 global clock |