EPM51929C vs EPM5192AGC84-20 Comparison

Detailed side-by-side comparison of EPM51929C by Intel and EPM5192AGC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM51929C EPM5192AGC84-20
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.40 $41.20
Device Family MAX 5000 β€”
Device Type EPLD (Erasable Programmable Logic Device) β€”
Architecture Multi-array matrix (PAL-based macrocells) β€”
Logic Density [DATA_NEEDED: usable gates] β€”
Number of Macrocells [DATA_NEEDED: macrocell count] β€”
Number of Pins [DATA_NEEDED: pin count] β€”
Package Type [DATA_NEEDED: package suffix - C denotes commercial temperature grade] β€”
Technology CMOS EPROM β€”
Programmability UV-erasable, JEDEC fuse map β€”
Operating Temperature Commercial (0C to +70C) β€”
Supply Voltage [DATA_NEEDED: VCC range] [DATA_NEEDED: VCC range]
Propagation Delay [DATA_NEEDED: tpd specification] β€”
Maximum Toggle Frequency [DATA_NEEDED: fmax] β€”
Mounting Type Surface Mount or Through-Hole (package dependent) Through-Hole (Pin Grid Array socket)
RoHS Status unknown [DATA_NEEDED: RoHS compliance]
Lead-Free unknown β€”
MSL Level [DATA_NEEDED] β€”
Product Type β€” Complex Programmable Logic Device (CPLD)
Family β€” MAX 5000
Macrocells β€” 192
User I/O Pins β€” 64
Dedicated Inputs β€” 7
Logic Gates (typical) β€” [DATA_NEEDED: typical gate count]
Maximum Clock Frequency (fMAX) β€” 66.7 MHz
Pin-to-Pin Delay (tPD) β€” 20 ns
Speed Grade β€” -20
Package β€” 84-pin Ceramic Pin Grid Array (CPGA, WPGA)
Package Code β€” WPGA
Erasure Method β€” UV-Erasable (with OTP window)
Process Technology β€” CMOS
Operating Temperature Grade β€” Commercial
I/O Standard β€” 5V CMOS / TTL compatible

Datasheets & Resources

Browse All Products Create BOM Request Quote