EPM51929C vs EPM5192AGC84-20 Comparison

Detailed side-by-side comparison of EPM51929C by Intel and EPM5192AGC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM51929C EPM5192AGC84-20
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Device Family MAX 5000 —
Device Type EPLD (Erasable Programmable Logic Device) —
Architecture Multi-array matrix (PAL-based macrocells) —
Logic Density [DATA_NEEDED: usable gates] —
Number of Macrocells [DATA_NEEDED: macrocell count] —
Number of Pins [DATA_NEEDED: pin count] —
Package Type [DATA_NEEDED: package suffix - C denotes commercial temperature grade] —
Technology CMOS EPROM —
Programmability UV-erasable, JEDEC fuse map —
Operating Temperature Commercial (0C to +70C) —
Supply Voltage [DATA_NEEDED: VCC range] [DATA_NEEDED: VCC range]
Propagation Delay [DATA_NEEDED: tpd specification] —
Maximum Toggle Frequency [DATA_NEEDED: fmax] —
Mounting Type Surface Mount or Through-Hole (package dependent) Through-Hole (Pin Grid Array socket)
RoHS Status unknown [DATA_NEEDED: RoHS compliance]
Lead-Free unknown —
MSL Level [DATA_NEEDED] —
Product Type — Complex Programmable Logic Device (CPLD)
Family — MAX 5000
Macrocells — 192
User I/O Pins — 64
Dedicated Inputs — 7
Logic Gates (typical) — [DATA_NEEDED: typical gate count]
Maximum Clock Frequency (fMAX) — 66.7 MHz
Pin-to-Pin Delay (tPD) — 20 ns
Speed Grade — -20
Package — 84-pin Ceramic Pin Grid Array (CPGA, WPGA)
Package Code — WPGA
Erasure Method — UV-Erasable (with OTP window)
Process Technology — CMOS
Operating Temperature Grade — Commercial
I/O Standard — 5V CMOS / TTL compatible

Datasheets & Resources

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