EPM51929C vs EPM5192AGC84-20 对比

详细并排对比 EPM51929C 出自 Intel 和 EPM5192AGC84-20 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM51929C EPM5192AGC84-20
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $9.40 $41.20
Device Family MAX 5000 —
Device Type EPLD (Erasable Programmable Logic Device) —
Architecture Multi-array matrix (PAL-based macrocells) —
Logic Density [DATA_NEEDED: usable gates] —
Number of Macrocells [DATA_NEEDED: macrocell count] —
引脚数 [DATA_NEEDED: pin count] —
Package Type [DATA_NEEDED: package suffix - C denotes commercial temperature grade] —
Technology CMOS EPROM —
Programmability UV-erasable, JEDEC fuse map —
工作温度 Commercial (0C to +70C) —
电源电压 [DATA_NEEDED: VCC range] [DATA_NEEDED: VCC range]
Propagation Delay [DATA_NEEDED: tpd specification] —
Maximum Toggle Frequency [DATA_NEEDED: fmax] —
安装类型 Surface Mount or Through-Hole (package dependent) Through-Hole (Pin Grid Array socket)
RoHS 状态 unknown [DATA_NEEDED: RoHS compliance]
Lead-Free unknown —
MSL 等级 [DATA_NEEDED] —
Product Type — Complex Programmable Logic Device (CPLD)
Family — MAX 5000
Macrocells — 192
User I/O Pins — 64
Dedicated Inputs — 7
Logic Gates (typical) — [DATA_NEEDED: typical gate count]
Maximum Clock Frequency (fMAX) — 66.7 MHz
Pin-to-Pin Delay (tPD) — 20 ns
Speed Grade — -20
封装 — 84-pin Ceramic Pin Grid Array (CPGA, WPGA)
Package Code — WPGA
Erasure Method — UV-Erasable (with OTP window)
Process Technology — CMOS
Operating Temperature Grade — Commercial
I/O Standard — 5V CMOS / TTL compatible

数据手册与资源

浏览全部产品 创建 BOM 获取报价