EPM51929C vs EPM5192AGC84-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM51929C sa pamamagitan ng Intel at EPM5192AGC84-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM51929C EPM5192AGC84-20
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family MAX 5000 —
Device Type EPLD (Erasable Programmable Logic Device) —
Architecture Multi-array matrix (PAL-based macrocells) —
Logic Density [DATA_NEEDED: usable gates] —
Number of Macrocells [DATA_NEEDED: macrocell count] —
Bilang ng Pins [DATA_NEEDED: pin count] —
Package Type [DATA_NEEDED: package suffix - C denotes commercial temperature grade] —
Technology CMOS EPROM —
Programmability UV-erasable, JEDEC fuse map —
Temperature na Operasyon Commercial (0C to +70C) —
Volte ng Pagbibigay [DATA_NEEDED: VCC range] [DATA_NEEDED: VCC range]
Propagation Delay [DATA_NEEDED: tpd specification] —
Maximum Toggle Frequency [DATA_NEEDED: fmax] —
Uri ng Pagpapasok Surface Mount or Through-Hole (package dependent) Through-Hole (Pin Grid Array socket)
Tindminan RoHS unknown [DATA_NEEDED: RoHS compliance]
Lead-Free unknown —
Level ng MSL [DATA_NEEDED] —
Product Type — Complex Programmable Logic Device (CPLD)
Family — MAX 5000
Macrocells — 192
User I/O Pins — 64
Dedicated Inputs — 7
Logic Gates (typical) — [DATA_NEEDED: typical gate count]
Maximum Clock Frequency (fMAX) — 66.7 MHz
Pin-to-Pin Delay (tPD) — 20 ns
Speed Grade — -20
Packhaging — 84-pin Ceramic Pin Grid Array (CPGA, WPGA)
Package Code — WPGA
Erasure Method — UV-Erasable (with OTP window)
Process Technology — CMOS
Operating Temperature Grade — Commercial
I/O Standard — 5V CMOS / TTL compatible

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita