EPM5192AGC84-20 vs EPM5192ALC84-15 Comparison

Detailed side-by-side comparison of EPM5192AGC84-20 by Altera and EPM5192ALC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192AGC84-20 EPM5192ALC84-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $41.20 $13.20
Product Type Complex Programmable Logic Device (CPLD) β€”
Family MAX 5000 β€”
Macrocells 192 192
User I/O Pins 64 64
Dedicated Inputs 7 7
Logic Gates (typical) [DATA_NEEDED: typical gate count] β€”
Maximum Clock Frequency (fMAX) 66.7 MHz β€”
Pin-to-Pin Delay (tPD) 20 ns β€”
Speed Grade -20 β€”
Package 84-pin Ceramic Pin Grid Array (CPGA, WPGA) 84-pin PLCC (QCCJ, J-bend ceramic)
Package Code WPGA QCCJ
Erasure Method UV-Erasable (with OTP window) β€”
Process Technology CMOS CMOS (EPROM-based)
Operating Temperature Grade Commercial Commercial
Supply Voltage [DATA_NEEDED: VCC range] β€”
I/O Standard 5V CMOS / TTL compatible β€”
RoHS Status [DATA_NEEDED: RoHS compliance] β€”
Mounting Type Through-Hole (Pin Grid Array socket) β€”
Device Family β€” MAX 5000 (EPM5192)
Device Type β€” CPLD / UV-Erasable / OTP Complex PLD
Propagation Delay (tPD) β€” 15 ns
Propagation Delay (Industry Variant) β€” 25 ns (per MicrochipUSA listing)
Supply Voltage (VCC) β€” 4.75 V to 5.25 V (nominal 5 V)
Programmability β€” UV-erasable window / OTP
Terminal Form β€” J-BEND
Package Shape β€” SQUARE
Architecture β€” Programmable Logic Array + Macrocell Registers + PIA interconnect

Datasheets & Resources

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