EPM5192AGC84-20 vs EPM5192ALC84-15 对比

详细并排对比 EPM5192AGC84-20 出自 Altera 和 EPM5192ALC84-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192AGC84-20 EPM5192ALC84-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $41.20 $13.20
Product Type Complex Programmable Logic Device (CPLD) —
Family MAX 5000 —
Macrocells 192 192
User I/O Pins 64 64
Dedicated Inputs 7 7
Logic Gates (typical) [DATA_NEEDED: typical gate count] —
Maximum Clock Frequency (fMAX) 66.7 MHz —
Pin-to-Pin Delay (tPD) 20 ns —
Speed Grade -20 —
封装 84-pin Ceramic Pin Grid Array (CPGA, WPGA) 84-pin PLCC (QCCJ, J-bend ceramic)
Package Code WPGA QCCJ
Erasure Method UV-Erasable (with OTP window) —
Process Technology CMOS CMOS (EPROM-based)
Operating Temperature Grade Commercial Commercial
电源电压 [DATA_NEEDED: VCC range] —
I/O Standard 5V CMOS / TTL compatible —
RoHS 状态 [DATA_NEEDED: RoHS compliance] —
安装类型 Through-Hole (Pin Grid Array socket) —
Device Family — MAX 5000 (EPM5192)
Device Type — CPLD / UV-Erasable / OTP Complex PLD
Propagation Delay (tPD) — 15 ns
Propagation Delay (Industry Variant) — 25 ns (per MicrochipUSA listing)
Supply Voltage (VCC) — 4.75 V to 5.25 V (nominal 5 V)
Programmability — UV-erasable window / OTP
Terminal Form — J-BEND
Package Shape — SQUARE
Architecture — Programmable Logic Array + Macrocell Registers + PIA interconnect

数据手册与资源

浏览全部产品 创建 BOM 获取报价