EPM5192AJC84-20 vs EPM5192AGC84-20 Comparison
Detailed side-by-side comparison of EPM5192AJC84-20 by Altera and EPM5192AGC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 Obsolete
Specification Comparison
| Parameter | EPM5192AJC84-20 | EPM5192AGC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $19.20 | $41.20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-erasable/OTP Complex PLD (CPLD) | β |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 33 ns (speed grade -20) | β |
| Maximum Clock Frequency | 66.7 MHz | β |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V | β |
| Dedicated Inputs | 7 | 7 |
| User I/O Lines | 64 | β |
| Process Technology | CMOS, UV-erasable EEPROM | CMOS |
| Package | 84-pin PLCC J-Lead (WQCCJ, J84) | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Operating Temperature Grade | Commercial | Commercial |
| Mounting Type | Surface Mount (J-Lead) | Through-Hole (Pin Grid Array socket) |
| MSL Level | [DATA_NEEDED: MSL level] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Programming Tool | Altera MAX+PLUS II / Quartus (legacy) | β |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | β |
| Product Type | β | Complex Programmable Logic Device (CPLD) |
| User I/O Pins | β | 64 |
| Logic Gates (typical) | β | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | β | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | β | 20 ns |
| Speed Grade | β | -20 |
| Package Code | β | WPGA |
| Erasure Method | β | UV-Erasable (with OTP window) |
| Supply Voltage | β | [DATA_NEEDED: VCC range] |
| I/O Standard | β | 5V CMOS / TTL compatible |