EPM5192GC-2 vs EPM5192GC-1 Comparison

Detailed side-by-side comparison of EPM5192GC-2 by Altera and EPM5192GC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192GC-2 EPM5192GC-1
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $92.00 $17.85
Family MAX 5000 MAX 5000 (Classic)
Macrocells 192 192
Logic Array Blocks 16 (LABs of 16 macrocells each) β€”
Usable I/O Pins [DATA_NEEDED: exact user I/O count for PGA package] β€”
Propagation Delay (tPD) 12 ns typical (-2 grade) β€”
Counter Frequency 100 MHz minimum β€”
Supply Voltage (VCC) 5 V nominal 4.75 V to 5.25 V
Technology CMOS EPROM β€”
Programmable Technology UV-erasable / one-time programmable β€”
Programming Toolchain Altera MAX+PLUS II β€”
Package Type Pin Grid Array (PGA), ceramic β€”
Operating Temperature Commercial (0C to +70C) [DATA_NEEDED: operating temperature grade]
Speed Grade -2 β€”
RoHS Status Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) [DATA_NEEDED: RoHS status]
Mounting Type Through-hole (PGA socket) Through-Hole (PGA)
Logic Type β€” CPLD (Complex Programmable Logic Device)
Usable Gates β€” 3,750
Logic Array Blocks (LABs) β€” 12
Dedicated Inputs β€” 7
User I/O Pins β€” 64
Maximum Propagation Delay (tPD) β€” 40 ns
Maximum Frequency (fMAX) β€” 62.5 MHz
Process Technology β€” CMOS, UV-erasable / OTP
Package β€” 100-pin Ceramic PGA (GC)
Configuration Method β€” UV-Erase / One-Time Programmable
Interconnect β€” Peripheral Interconnect Array (PIA)

Datasheets & Resources

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