EPM5192GC-2 vs EPM5192GC-1 Comparación
Comparación detallada lado a lado de EPM5192GC-2 por Altera y EPM5192GC-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192GC-2 | EPM5192GC-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $92,00 | $17,85 |
| Family | MAX 5000 | MAX 5000 (Classic) |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (LABs of 16 macrocells each) | — |
| Usable I/O Pins | [DATA_NEEDED: exact user I/O count for PGA package] | — |
| Propagation Delay (tPD) | 12 ns typical (-2 grade) | — |
| Counter Frequency | 100 MHz minimum | — |
| Supply Voltage (VCC) | 5 V nominal | 4.75 V to 5.25 V |
| Technology | CMOS EPROM | — |
| Programmable Technology | UV-erasable / one-time programmable | — |
| Programming Toolchain | Altera MAX+PLUS II | — |
| Package Type | Pin Grid Array (PGA), ceramic | — |
| Temperatura de funcionamiento | Commercial (0C to +70C) | [DATA_NEEDED: operating temperature grade] |
| Speed Grade | -2 | — |
| Estado RoHS | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) | [DATA_NEEDED: RoHS status] |
| Tipo de montaje | Through-hole (PGA socket) | Through-Hole (PGA) |
| Logic Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 3,750 |
| Logic Array Blocks (LABs) | — | 12 |
| Dedicated Inputs | — | 7 |
| User I/O Pins | — | 64 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Frequency (fMAX) | — | 62.5 MHz |
| Process Technology | — | CMOS, UV-erasable / OTP |
| Encapsulado | — | 100-pin Ceramic PGA (GC) |
| Configuration Method | — | UV-Erase / One-Time Programmable |
| Interconnect | — | Peripheral Interconnect Array (PIA) |