EPM5192GC-2 vs EPM5192GI84 Comparison

Detailed side-by-side comparison of EPM5192GC-2 by Altera and EPM5192GI84 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192GC-2 EPM5192GI84
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 5000 MAX 5000
Macrocells 192 192
Logic Array Blocks 16 (LABs of 16 macrocells each) [DATA_NEEDED: number of LABs]
Usable I/O Pins [DATA_NEEDED: exact user I/O count for PGA package] —
Propagation Delay (tPD) 12 ns typical (-2 grade) —
Counter Frequency 100 MHz minimum —
Supply Voltage (VCC) 5 V nominal —
Technology CMOS EPROM —
Programmable Technology UV-erasable / one-time programmable —
Programming Toolchain Altera MAX+PLUS II —
Package Type Pin Grid Array (PGA), ceramic —
Operating Temperature Commercial (0C to +70C) —
Speed Grade -2 —
RoHS Status Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) [DATA_NEEDED: most legacy PGA parts are non-RoHS]
Mounting Type Through-hole (PGA socket) Through-Hole (PGA socket or PCB pin/peg)
Device Type — UV-Erasable / OTP Complex PLD (CPLD)
Package — 84-pin PGA (WPGA, square, through-hole, pin/peg terminals)
Package Code — WPGA
Operating Voltage (VCC) — 5 V (typical)
I/O Logic Compatibility — TTL
Temperature Grade — Industrial
Programmable Flip-Flop Modes — D, T, JK, SR
Programmability — UV-erasable (windowed) / OTP
Programming File Format — JEDEC map via MAX+PLUS II / A+PLUS
Propagation Delay — [DATA_NEEDED: tPD in ns]
Max User I/O Pins — [DATA_NEEDED: usable I/O count for this package]
Operating Temperature Range — -40 C to +85 C (industrial)
Lead-Free — [DATA_NEEDED: legacy part, likely contains lead]
Number of Terminals — 84
Terminal Form — PIN/PEG
Package Shape — SQUARE

Datasheets & Resources

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