EPM5192GC-2 vs EPM5192GI84 比較
詳細並排比較 EPM5192GC-2 由 Altera 與 EPM5192GI84 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192GC-2 | EPM5192GI84 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (LABs of 16 macrocells each) | [DATA_NEEDED: number of LABs] |
| Usable I/O Pins | [DATA_NEEDED: exact user I/O count for PGA package] | — |
| Propagation Delay (tPD) | 12 ns typical (-2 grade) | — |
| Counter Frequency | 100 MHz minimum | — |
| Supply Voltage (VCC) | 5 V nominal | — |
| Technology | CMOS EPROM | — |
| Programmable Technology | UV-erasable / one-time programmable | — |
| Programming Toolchain | Altera MAX+PLUS II | — |
| Package Type | Pin Grid Array (PGA), ceramic | — |
| 工作溫度 | Commercial (0C to +70C) | — |
| Speed Grade | -2 | — |
| RoHS 狀態 | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) | [DATA_NEEDED: most legacy PGA parts are non-RoHS] |
| 安裝類型 | Through-hole (PGA socket) | Through-Hole (PGA socket or PCB pin/peg) |
| Device Type | — | UV-Erasable / OTP Complex PLD (CPLD) |
| 封裝 | — | 84-pin PGA (WPGA, square, through-hole, pin/peg terminals) |
| Package Code | — | WPGA |
| Operating Voltage (VCC) | — | 5 V (typical) |
| I/O Logic Compatibility | — | TTL |
| Temperature Grade | — | Industrial |
| Programmable Flip-Flop Modes | — | D, T, JK, SR |
| Programmability | — | UV-erasable (windowed) / OTP |
| Programming File Format | — | JEDEC map via MAX+PLUS II / A+PLUS |
| Propagation Delay | — | [DATA_NEEDED: tPD in ns] |
| Max User I/O Pins | — | [DATA_NEEDED: usable I/O count for this package] |
| 工作溫度範圍 | — | -40 C to +85 C (industrial) |
| Lead-Free | — | [DATA_NEEDED: legacy part, likely contains lead] |
| Number of Terminals | — | 84 |
| Terminal Form | — | PIN/PEG |
| Package Shape | — | SQUARE |