EPM5192JC-2 vs EPM5192JI-2 Comparison
Detailed side-by-side comparison of EPM5192JC-2 by Altera and EPM5192JI-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192JC-2 | EPM5192JI-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-erasable Programmable Logic Device (PLD) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 12 |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 45 ns | — |
| Maximum Clock Frequency | 40 MHz | — |
| Process Technology | CMOS | CMOS EPROM |
| Package | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) | JLCC-68 (J-Lead Ceramic) |
| Mounting Type | Surface Mount | Surface Mount |
| Number of Terminals | 84 | — |
| Programming Method | UV-erase / EPROM | — |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | Non-compliant (ceramic JLCC, contains lead) |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 5000 |
| Flip-Flops | — | 192 |
| Speed Grade | — | -2 |
| Operating Temperature | — | 0C to +70C (commercial) |
| Programming Technology | — | UV-Erasable EPROM |
| Architecture | — | Sum-of-products with Programmable Interconnect Array (PIA) |
| Supply Voltage | — | 5 V (typical) |
| Lifecycle Status | — | Obsolete (legacy Altera MAX 5000 family) |