EPM5192JC-2 vs EPM5192JI-2 比較
詳細並排比較 EPM5192JC-2 由 Altera 與 EPM5192JI-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JC-2 | EPM5192JI-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-erasable Programmable Logic Device (PLD) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 12 |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 45 ns | — |
| 最大時脈頻率 | 40 MHz | — |
| Process Technology | CMOS | CMOS EPROM |
| 封裝 | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) | JLCC-68 (J-Lead Ceramic) |
| 安裝類型 | Surface Mount | Surface Mount |
| Number of Terminals | 84 | — |
| Programming Method | UV-erase / EPROM | — |
| 工作溫度範圍 | [DATA_NEEDED: operating temperature range] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Non-compliant (ceramic JLCC, contains lead) |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 5000 |
| Flip-Flops | — | 192 |
| Speed Grade | — | -2 |
| 工作溫度 | — | 0C to +70C (commercial) |
| Programming Technology | — | UV-Erasable EPROM |
| Architecture | — | Sum-of-products with Programmable Interconnect Array (PIA) |
| 供應電壓 | — | 5 V (typical) |
| 生命週期狀態 | — | Obsolete (legacy Altera MAX 5000 family) |