EPM5192JC-2 vs EPM5192JI-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC-2 sa pamamagitan ng Altera at EPM5192JI-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192JC-2 | EPM5192JI-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-erasable Programmable Logic Device (PLD) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 12 |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 45 ns | — |
| Maksimum na Taktiko ng Oras | 40 MHz | — |
| Process Technology | CMOS | CMOS EPROM |
| Packhaging | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) | JLCC-68 (J-Lead Ceramic) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Number of Terminals | 84 | — |
| Programming Method | UV-erase / EPROM | — |
| Hanay ng Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (ceramic JLCC, contains lead) |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 5000 |
| Flip-Flops | — | 192 |
| Speed Grade | — | -2 |
| Temperature na Operasyon | — | 0C to +70C (commercial) |
| Programming Technology | — | UV-Erasable EPROM |
| Architecture | — | Sum-of-products with Programmable Interconnect Array (PIA) |
| Volte ng Pagbibigay | — | 5 V (typical) |
| Katayuan ng Lifecycle | — | Obsolete (legacy Altera MAX 5000 family) |