EPM5192LC-25 vs EPM5192LC Comparison

Detailed side-by-side comparison of EPM5192LC-25 by Altera and EPM5192LC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192LC-25 EPM5192LC
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $55.00 $28.40
Product Type CPLD (Complex Programmable Logic Device) β€”
Family MAX 5000 MAX 7000S
Macrocells 192 192
Logic Elements 192 (1 macrocell β‰ˆ 1 LE in MAX 5000 architecture) β€”
Pin-to-Pin Delay (tPD) 25 ns β€”
Speed Grade -25 (25 ns) β€”
Package JLCC-84 (ceramic J-lead chip carrier) JLCC-68 (windowed ceramic, LC suffix)
Mounting Type Surface Mount Surface Mount
Programmable Technology UV-erasable / OTP (EPROM-based) β€”
Programming Interface JTAG / Altera programming hardware (legacy) JTAG (ByteBlaster-compatible)
Operating Temperature 0C to +70C (commercial) β€”
Supply Voltage 5 V (typical, MAX 5000) β€”
I/O Standard TTL-compatible β€”
Configuration Memory Non-volatile EPROM (on-chip) β€”
Manufacturer Altera Corporation (now Intel PSG) β€”
RoHS Status Unknown (legacy ceramic package typically non-RoHS) [DATA_NEEDED: RoHS status]
Logic Array Blocks (LABs) β€” 12
User I/O Pins β€” 64
Dedicated Inputs β€” 7
Global Clock Inputs β€” 1
Propagation Delay (tPD) β€” 55 ns (typical, commercial)
Maximum Clock Frequency (fMAX) β€” 50 MHz
Supply Voltage (VCC) β€” 4.75 V to 5.25 V (nominal 5 V)
Process Technology β€” CMOS, UV-erasable/OTP EPROM configuration
Programmable Interconnect β€” Programmable Interconnect Array (PIA), fixed delay
Boundary-Scan Support β€” JTAG IEEE 1149.1
Operating Temperature (commercial) β€” 0C to +70C

Datasheets & Resources

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