EPM5192LC-25 vs EPM5192LC Vergleich

Detaillierter Direktvergleich von EPM5192LC-25 von Altera und EPM5192LC von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter EPM5192LC-25 EPM5192LC
Marke Altera Altera
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Obsolete
Lagerstatus In Stock In Stock
Stückpreis (USD) $55,00 $28,40
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 5000 MAX 7000S
Macrocells 192 192
Logic Elements 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) —
Pin-to-Pin Delay (tPD) 25 ns —
Speed Grade -25 (25 ns) —
Gehäuse JLCC-84 (ceramic J-lead chip carrier) JLCC-68 (windowed ceramic, LC suffix)
Montageart Surface Mount Surface Mount
Programmable Technology UV-erasable / OTP (EPROM-based) —
Programming Interface JTAG / Altera programming hardware (legacy) JTAG (ByteBlaster-compatible)
Betriebstemperatur 0C to +70C (commercial) —
Versorgungsspannung 5 V (typical, MAX 5000) —
I/O Standard TTL-compatible —
Configuration Memory Non-volatile EPROM (on-chip) —
Manufacturer Altera Corporation (now Intel PSG) —
RoHS-Status Unknown (legacy ceramic package typically non-RoHS) [DATA_NEEDED: RoHS status]
Logic Array Blocks (LABs) — 12
User I/O Pins — 64
Dedicated Inputs — 7
Global Clock Inputs — 1
Propagation Delay (tPD) — 55 ns (typical, commercial)
Maximum Clock Frequency (fMAX) — 50 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (nominal 5 V)
Process Technology — CMOS, UV-erasable/OTP EPROM configuration
Programmable Interconnect — Programmable Interconnect Array (PIA), fixed delay
Boundary-Scan Support — JTAG IEEE 1149.1
Operating Temperature (commercial) — 0C to +70C

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