EPM5192LC2 vs EPM5192LC Comparison
Detailed side-by-side comparison of EPM5192LC2 by Intel and EPM5192LC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC2 | EPM5192LC |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.40 | $28.40 |
| Family | MAX 5000 | MAX 7000S |
| Device Type | EPLD (Erasable Programmable Logic Device) | β |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | 64 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Dedicated Inputs | 7 | 7 |
| External Clock Inputs | 1 | β |
| Propagation Delay (tpd) | 45 ns (LC-2 speed grade) | β |
| Maximum Clock Frequency | 50 MHz | β |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (nominal 5 V) |
| Process Technology | CMOS | CMOS, UV-erasable/OTP EPROM configuration |
| Package | PQCC-84 (84-pin Plastic J-Lead Chip Carrier) | JLCC-68 (windowed ceramic, LC suffix) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | β |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA), fixed delay |
| Reprogrammability | Windowed UV-erasable (ceramic package variants) / One-time programmable (plastic) | β |
| Global Clock Inputs | β | 1 |
| Propagation Delay (tPD) | β | 55 ns (typical, commercial) |
| Maximum Clock Frequency (fMAX) | β | 50 MHz |
| Boundary-Scan Support | β | JTAG IEEE 1149.1 |
| Programming Interface | β | JTAG (ByteBlaster-compatible) |
| Operating Temperature (commercial) | β | 0C to +70C |
| RoHS Status | β | [DATA_NEEDED: RoHS status] |