EPM5192LC2 vs EPM5192LC Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC2 sa pamamagitan ng Intel at EPM5192LC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192LC2 | EPM5192LC |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 7000S |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | 64 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Dedicated Inputs | 7 | 7 |
| External Clock Inputs | 1 | — |
| Propagation Delay (tpd) | 45 ns (LC-2 speed grade) | — |
| Maksimum na Taktiko ng Oras | 50 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (nominal 5 V) |
| Process Technology | CMOS | CMOS, UV-erasable/OTP EPROM configuration |
| Packhaging | PQCC-84 (84-pin Plastic J-Lead Chip Carrier) | JLCC-68 (windowed ceramic, LC suffix) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA), fixed delay |
| Reprogrammability | Windowed UV-erasable (ceramic package variants) / One-time programmable (plastic) | — |
| Global Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 55 ns (typical, commercial) |
| Maximum Clock Frequency (fMAX) | — | 50 MHz |
| Boundary-Scan Support | — | JTAG IEEE 1149.1 |
| Programming Interface | — | JTAG (ByteBlaster-compatible) |
| Operating Temperature (commercial) | — | 0C to +70C |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |