EPM5192LC84 vs EPM5192LC Comparison
Detailed side-by-side comparison of EPM5192LC84 by Altera and EPM5192LC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5192LC84
EPM5192LC84 - 192-Cell OTP PLD, 55ns, LCC-84 | Altera / Cypress
EPM5192LC84 ObsoleteSpecification Comparison
| Parameter | EPM5192LC84 | EPM5192LC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $15.95 | $28.40 |
| Product Type | Complex Programmable Logic Device (CPLD) | β |
| Family | MAX 5000 | MAX 7000S |
| Macrocells (Logic Cells) | 192 | β |
| Propagation Delay (tPD) | 55 ns | 55 ns (typical, commercial) |
| Process Technology | CMOS | CMOS, UV-erasable/OTP EPROM configuration |
| Programmability | OTP / UV-Erasable | β |
| Package | LCC-84 (PQCC84, MS-018) | JLCC-68 (windowed ceramic, LC suffix) |
| Pin Count | 84 | β |
| Mounting Type | Surface Mount (Socket-compatible) | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | β |
| Supply Voltage | [DATA_NEEDED: VCC range] | β |
| User I/O | [DATA_NEEDED: max user I/O count] | β |
| Configuration Memory | EPROM / UV-Erasable | β |
| Programming Interface | JTAG / Altera legacy (MAX+PLUS II baseline) | JTAG (ByteBlaster-compatible) |
| RoHS Status | unknown | [DATA_NEEDED: RoHS status] |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Macrocells | β | 192 |
| Logic Array Blocks (LABs) | β | 12 |
| User I/O Pins | β | 64 |
| Dedicated Inputs | β | 7 |
| Global Clock Inputs | β | 1 |
| Maximum Clock Frequency (fMAX) | β | 50 MHz |
| Supply Voltage (VCC) | β | 4.75 V to 5.25 V (nominal 5 V) |
| Programmable Interconnect | β | Programmable Interconnect Array (PIA), fixed delay |
| Boundary-Scan Support | β | JTAG IEEE 1149.1 |
| Operating Temperature (commercial) | β | 0C to +70C |