EPM5192LC84 - 192-Cell OTP PLD, 55ns, LCC-84 | Altera / Cypress
MPN: EPM5192LC84 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $21.75 | $2,175.00 |
| 500 | $18.4 | $9,200.00 |
| 1,000 | $15.95 | $15,950.00 |
Drop-in alternatives for EPM5192LC84 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM5192GM/883B
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$118 / Unit
View Datasheet βEPM5192LC
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$28.4 / Unit
View Datasheet βEPM5192LC-1
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$14.2 / Unit
View Datasheet βEPM5192GC84-1
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$14.2 / Unit
View Datasheet βEPM5192GI84
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$19.8 / Unit
View Datasheet βXC9572XL-10VQG84
β Drop-Inπ Reference alternative (not in catalog)
XC95144XL-10VQG84
β Drop-Inπ Reference alternative (not in catalog)
EPM5192LC84 Maximum Ratings & Electrical Characteristics
| Product Type | Complex Programmable Logic Device (CPLD) |
| Family | MAX 5000 |
| Macrocells (Logic Cells) | 192 |
| Propagation Delay (tPD) | 55 ns |
| Process Technology | CMOS |
| Programmability | OTP / UV-Erasable |
| Package | LCC-84 (PQCC84, MS-018) |
| Pin Count | 84 |
| Mounting Type | Surface Mount (Socket-compatible) |
| Configuration Memory | EPROM / UV-Erasable |
| Programming Interface | JTAG / Altera legacy (MAX+PLUS II baseline) |
| RoHS Status | unknown |
EPM5192LC84 Pin Configuration
| Pin 1 | GND β Ground reference |
| Pin 2 | I/O β User I/O - macrocell I/O pin |
| Pin 3 | I/O β User I/O - macrocell I/O pin |
| Pin 4 | I/O β User I/O - macrocell I/O pin |
| Pin 5 | I/O β User I/O - macrocell I/O pin |
| Pin 6 | I/O β User I/O - macrocell I/O pin |
| Pin 7 | I/O β User I/O - macrocell I/O pin |
| Pin 8 | I/O β User I/O - macrocell I/O pin |
| Pin 9 | I/O β User I/O - macrocell I/O pin |
| Pin 10 | I/O β User I/O - macrocell I/O pin |
| Pin 11 | GND β Ground reference |
| Pin 12 | I/O β User I/O - macrocell I/O pin |
| Pin 13 | I/O β User I/O - macrocell I/O pin |
| Pin 14 | I/O β User I/O - macrocell I/O pin |
| Pin 15 | I/O β User I/O - macrocell I/O pin |
| Pin 16 | I/O β User I/O - macrocell I/O pin |
| Pin 17 | I/O β User I/O - macrocell I/O pin |
| Pin 18 | I/O β User I/O - macrocell I/O pin |
| Pin 19 | I/O β User I/O - macrocell I/O pin |
| Pin 20 | I/O β User I/O - macrocell I/O pin |
| Pin 21 | I/O β User I/O - macrocell I/O pin |
| Pin 22 | GND β Ground reference |
| Pin 23 | I/O β User I/O - macrocell I/O pin |
| Pin 24 | I/O β User I/O - macrocell I/O pin |
| Pin 25 | I/O β User I/O - macrocell I/O pin |
| Pin 26 | I/O β User I/O - macrocell I/O pin |
| Pin 27 | I/O β User I/O - macrocell I/O pin |
| Pin 28 | I/O β User I/O - macrocell I/O pin |
| Pin 29 | I/O β User I/O - macrocell I/O pin |
| Pin 30 | I/O β User I/O - macrocell I/O pin |
| Pin 31 | I/O β User I/O - macrocell I/O pin |
| Pin 32 | I/O β User I/O - macrocell I/O pin |
| Pin 33 | GND β Ground reference |
| Pin 34 | I/O β User I/O - macrocell I/O pin |
| Pin 35 | I/O β User I/O - macrocell I/O pin |
| Pin 36 | I/O β User I/O - macrocell I/O pin |
| Pin 37 | I/O β User I/O - macrocell I/O pin |
| Pin 38 | I/O β User I/O - macrocell I/O pin |
| Pin 39 | I/O β User I/O - macrocell I/O pin |
| Pin 40 | I/O β User I/O - macrocell I/O pin |
| Pin 41 | I/O β User I/O - macrocell I/O pin |
| Pin 42 | I/O β User I/O - macrocell I/O pin |
| Pin 43 | I/O β User I/O - macrocell I/O pin |
| Pin 44 | GND β Ground reference |
| Pin 45 | I/O β User I/O - macrocell I/O pin |
| Pin 46 | I/O β User I/O - macrocell I/O pin |
| Pin 47 | I/O β User I/O - macrocell I/O pin |
| Pin 48 | I/O β User I/O - macrocell I/O pin |
| Pin 49 | I/O β User I/O - macrocell I/O pin |
| Pin 50 | I/O β User I/O - macrocell I/O pin |
| Pin 51 | I/O β User I/O - macrocell I/O pin |
| Pin 52 | I/O β User I/O - macrocell I/O pin |
| Pin 53 | I/O β User I/O - macrocell I/O pin |
| Pin 54 | I/O β User I/O - macrocell I/O pin |
| Pin 55 | GND β Ground reference |
| Pin 56 | I/O β User I/O - macrocell I/O pin |
| Pin 57 | I/O β User I/O - macrocell I/O pin |
| Pin 58 | I/O β User I/O - macrocell I/O pin |
| Pin 59 | I/O β User I/O - macrocell I/O pin |
| Pin 60 | I/O β User I/O - macrocell I/O pin |
| Pin 61 | I/O β User I/O - macrocell I/O pin |
| Pin 62 | I/O β User I/O - macrocell I/O pin |
| Pin 63 | I/O β User I/O - macrocell I/O pin |
| Pin 64 | I/O β User I/O - macrocell I/O pin |
| Pin 65 | I/O β User I/O - macrocell I/O pin |
| Pin 66 | GND β Ground reference |
| Pin 67 | I/O β User I/O - macrocell I/O pin |
| Pin 68 | I/O β User I/O - macrocell I/O pin |
| Pin 69 | I/O β User I/O - macrocell I/O pin |
| Pin 70 | I/O β User I/O - macrocell I/O pin |
| Pin 71 | I/O β User I/O - macrocell I/O pin |
| Pin 72 | I/O β User I/O - macrocell I/O pin |
| Pin 73 | I/O β User I/O - macrocell I/O pin |
| Pin 74 | I/O β User I/O - macrocell I/O pin |
| Pin 75 | I/O β User I/O - macrocell I/O pin |
| Pin 76 | I/O β User I/O - macrocell I/O pin |
| Pin 77 | GND β Ground reference |
| Pin 78 | I/O β User I/O - macrocell I/O pin |
| Pin 79 | I/O β User I/O - macrocell I/O pin |
| Pin 80 | I/O β User I/O - macrocell I/O pin |
| Pin 81 | I/O β User I/O - macrocell I/O pin |
| Pin 82 | I/O β User I/O - macrocell I/O pin |
| Pin 83 | VCC β Positive supply (5 V typical) |
| Pin 84 | VCC β Positive supply (5 V typical) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5192LC84 is suitable for 6 applications: Legacy Microprocessor Bus Decoding, Industrial Glue-Logic Replacement, Telecom Backplane Control Logic, Avionics / Military Display and Control, Medical Imaging Front-End Logic, Test & Measurement Equipment Front Panel.
Legacy Microprocessor Bus Decoding
The EPM5192LC84 fits legacy 8086/68000/Z80 bus decoding applications because its 192 macrocells can absorb the full address-decoding plus chip-select logic for an entire system. The 55 ns propagation delay accommodates ISA-bus timing where the CPU asserts address lines and expects a stable chip-select within two clock edges. Its instant-on, non-volatile EPROM configuration eliminates the boot PROM required by an FPGA. With 84 I/O pins in the LCC-84 carrier, all address and chip-select signals are routed without external muxes.
Recommended
Industrial Glue-Logic Replacement
In industrial control backplanes, the EPM5192LC84 replaces dozens of 74LS/74F/74HC TTL packages with a single programmable part, reducing board area and BOM count. Its 192 macrocells handle complex state machines, encoder/decoder logic, and PWM generation for motor-control boards. The CMOS process gives low quiescent current and high noise immunity suitable for factory-floor environments with motors and relays. JTAG in-system programming allows field firmware updates via the test access port without removing the chip.
Recommended
Telecom Backplane Control Logic
The EPM5192LC84 was widely deployed in legacy telecom backplanes as line-card control logic, alarm encoders, and protocol translators. Its 55 ns propagation delay and CMOS drive strength match the backplane signalling of its era, while the LCC-84 package provides robust mechanical and thermal performance for central-office environments. The OTP configuration ensures deterministic boot, which telecom systems require for power-on self-test sequences. For new telecom designs, MAX V 5M240Z provides equivalent logic density in modern packages with flash configuration.
Recommended
Avionics / Military Display and Control
In avionics and military platforms the EPM5192LC84 served as display-driver control logic, encoder logic for MIL-STD-1553 interfaces, and redundant watchdog sequencers. The /883B screened variant (EPM5192GM/883B) provides the extended temperature and burn-in assurance required by avionics programs. The LCC-84 ceramic-compatible carrier withstands vibration and thermal cycling typical of flight environments. New avionics programs should consider RAD-tolerant Microsemi/Intel RTG4 FPGAs or modern MAX V for non-rad-tolerant subsystems.
Recommended
Medical Imaging Front-End Logic
The EPM5192LC84 was used in late-1990s/early-2000s medical imaging front-ends to perform scan-coordination state machines, beam-former timing, and detector read-out sequencing. The 192-macrocell capacity absorbs multi-state sequencers for CT, ultrasound, and X-ray subsystems. Its deterministic timing (no SRAM-based FPGA boot delay) supports real-time medical control loops. Modern medical designs should evaluate MAX V 5M240Z or MAX 10 (10M02) for active lifecycle, lower power, and IEC 61508 SIL support.
Recommended
Test & Measurement Equipment Front Panel
In bench-top T&M instruments (oscilloscopes, spectrum analyzers, signal generators), the EPM5192LC84 was used to implement front-panel key-scanning, range-relay sequencing, and display-multiplexing control. Its 84-pin LCC carrier exposes enough I/O for direct matrix-key drive without external muxes. The 55 ns delay fits human-interface refresh rates and range-switching sequencing. New instruments should consider MAX V or MAX 10, which add ADC blocks, internal flash, and active supply continuity through 2035+.
Recommended
Recommended Products Summary
Engineering reference data for EPM5192LC84 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5192GM/883B | EPM5192LC | EPM5192LC-1 | EPM5192GI84 | XC9572XL-10VQG84 | XC95144XL-10VQG84 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Xilinx | Xilinx |
| Package | LCC-84 (PQCC84) | LCC-84 (PQCC84) - same | LCC-84 (PQCC84) - same | LCC-84 (PQCC84) - same | LCC-84 (PQCC84) - same | LCC-84 (PQCC84) - same PLCC-84 footprint | LCC-84 (PQCC84) - same PLCC-84 footprint |
| Macrocells | 192 | 192 | 192 | 192 | 192 | 72 (-62%) | 144 (-25%) |
| Propagation Delay (tPD) | 55 ns | 55 ns | 55 ns | [DATA_NEEDED] | [DATA_NEEDED] | 10 ns | 10 ns |
| Configuration Memory | OTP/UV-EPROM | OTP/UV-EPROM | OTP/UV-EPROM | OTP/UV-EPROM | OTP/UV-EPROM | Flash (in-system reprogrammable) | Flash (in-system reprogrammable) |
| Programming Toolchain | MAX+PLUS II (legacy) | MAX+PLUS II (legacy) | MAX+PLUS II (legacy) | MAX+PLUS II (legacy) | MAX+PLUS II (legacy) | Xilinx ISE / iMPACT | Xilinx ISE / iMPACT |
| Lifecycle Status | Obsolete | Obsolete (MIL-grade legacy) | Obsolete | Obsolete | Obsolete | Mature (still limited supply) | Mature (still limited supply) |
| MIL-STD-883 Screening | No | Yes | No | No | No | No | No |
Key Differentiators
- Highest-density MAX 5000 member in LCC-84 (vs EPM5128LC)
- MIL-STD-883 sibling available with same die (vs EPM5192GM/883B)
- Pin-compatible socket migration to Xilinx (vs XC9572XL-10VQG84 / XC95144XL-10VQG84)
Design Notes
Estimated: When migrating from EPM5192LC84 to Xilinx XC9500XL, never assume pin-to-pin transparency. Both share a PLCC-84 carrier but the macrocell count differs (192 vs 72-144) and the pinout assignments are not identical. Engineers must regenerate the design in Xilinx ISE/WebPACK with full pin reassignment, then validate timing closure. The MAX+PLUS II toolchain does not target Xilinx parts and vice versa, so JEDEC/BIT/BEQ programming files from one vendor will not load onto the other.
Estimated: The PQCC84 (LCC-84) plastic carrier has theta_JA around 50-60 C/W in still air. At 5 V VCC and 192 active macrocells switching simultaneously, internal dissipation can reach 0.5-1.5 W, producing a 25-90 C junction rise above ambient. For continuous operation above 70 C ambient, ensure 100+ sq cm of copper pour under the package or specify the ceramic-windowed EPM5192GM variant for cooler operation. Industrial variants (EPM5192GI84) are screened to -40 C to +85 C.
Estimated: Place 0.1 uF decoupling capacitors within 5 mm of every VCC pin (pins 83 and 84 on EPM5192LC84). Add a 10 uF bulk tantalum or ceramic capacitor at the board entry point. The LCC-84 carrier exposes GND on pins 1, 11, 22, 33, 44, 55, 66, 77 - stitch these directly to a continuous ground plane for lowest ground-bounce on high-drive I/O toggles. Maintain 0.2-inch (5.08 mm) clearance between the LCC pads and signal traces for socketed installations.
Compliance Information
The EPM5192LC84 PQCC84 variant predates widespread RoHS compliance; PQCC84 (MS-018) is a tin-lead plastic carrier. Industrial/ceramic variants may be lead-free. MIL /883B variants (EPM5192GM/883B) typically do not claim RoHS. Verify by lot/date code and manufacturer C of C before use in RoHS-restricted assemblies.
