EPM7096LC84-7 vs EPM7096LC68-7 Comparison
Detailed side-by-side comparison of EPM7096LC84-7 by Intel and EPM7096LC68-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7096LC84-7 | EPM7096LC68-7 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 7000 | MAX 7000 |
| Macrocells | 96 | 96 |
| Logic Array Blocks (LABs) | 4 | 4 |
| User I/O Pins | 64 | 52 |
| Speed Grade (tPD) | 7.5 ns | — |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) | 68-pin J-Lead PLCC (LC68) |
| Mounting Type | Surface Mount | Surface Mount |
| Supply Voltage | 5.0 V | — |
| Programming Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Architecture | Second-generation MAX | EEPROM, second-generation MAX |
| I/O Logic Levels | 5.0 V TTL/CMOS-compatible | — |
| Operating Temperature | 0C to +70C (commercial, LC suffix) | -40C to +85C (industrial, typical) |
| RoHS Status | Non-compliant (original Altera product, leaded PLCC package) | Non-compliant (legacy 5V PLCC) |
| Lifecycle Status | Obsolete - PCN/PDN issued by Intel | — |
| Device Type | — | CPLD (EEPROM-based) |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Global Clock Pins | — | 6 |
| Process Technology | — | CMOS EEPROM |