EPM7096LC84-7 vs EPM7096LC68-7 比較
詳細並排比較 EPM7096LC84-7 由 Intel 與 EPM7096LC68-7 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM7096LC84-7 | EPM7096LC68-7 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 7000 | MAX 7000 |
| Macrocells | 96 | 96 |
| Logic Array Blocks (LABs) | 4 | 4 |
| User I/O Pins | 64 | 52 |
| Speed Grade (tPD) | 7.5 ns | — |
| 封裝 | 84-pin PLCC (Plastic Leaded Chip Carrier) | 68-pin J-Lead PLCC (LC68) |
| 安裝類型 | Surface Mount | Surface Mount |
| 供應電壓 | 5.0 V | — |
| Programming Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Architecture | Second-generation MAX | EEPROM, second-generation MAX |
| I/O Logic Levels | 5.0 V TTL/CMOS-compatible | — |
| 工作溫度 | 0C to +70C (commercial, LC suffix) | -40C to +85C (industrial, typical) |
| RoHS 狀態 | Non-compliant (original Altera product, leaded PLCC package) | Non-compliant (legacy 5V PLCC) |
| 生命週期狀態 | Obsolete - PCN/PDN issued by Intel | — |
| Device Type | — | CPLD (EEPROM-based) |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| In-System Programming | — | Yes (IEEE 1149.1 JTAG) |
| Global Clock Pins | — | 6 |
| Process Technology | — | CMOS EEPROM |