EPM7096LC84-7 - 96-Macrocell MAX 7000 CPLD, 7.5ns, PLCC-84 | Intel
MPN: EPM7096LC84-7 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $27.4 | $2,740.00 |
| 500 | $22.9 | $11,450.00 |
| 1,000 | $19.85 | $19,850.00 |
Drop-in alternatives for EPM7096LC84-7 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7096LC84-10
β Drop-Inβ In Stock
$5.1 / Unit
View Datasheet βEPM7096LC84-15
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEPM7096LC68-7
β Drop-Inβ In Stock
$9.95 / Unit
View Datasheet βEPM7096LC68-15
β Drop-Inβ In Stock
$7.2 / Unit
View Datasheet βEPM7128ELC84-7
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM7096LC84-7 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Macrocells | 96 |
| Logic Array Blocks (LABs) | 4 |
| User I/O Pins | 64 |
| Speed Grade (tPD) | 7.5 ns |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Mounting Type | Surface Mount |
| Supply Voltage | 5.0 V |
| Programming Technology | EEPROM (non-volatile) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Architecture | Second-generation MAX |
| I/O Logic Levels | 5.0 V TTL/CMOS-compatible |
| Operating Temperature | 0C to +70C (commercial, LC suffix) |
| RoHS Status | Non-compliant (original Altera product, leaded PLCC package) |
| Lifecycle Status | Obsolete - PCN/PDN issued by Intel |
EPM7096LC84-7 Pin Configuration
| Pin 1 | I/O β User I/O pin (macrocell input/output) |
| Pin 2 | I/O β User I/O pin (macrocell input/output) |
| Pin 3 | I/O β User I/O pin (macrocell input/output) |
| Pin 4 | I/O β User I/O pin (macrocell input/output) |
| Pin 5 | I/O β User I/O pin (macrocell input/output) |
| Pin 6 | I/O β User I/O pin (macrocell input/output) |
| Pin 7 | I/O β User I/O pin (macrocell input/output) |
| Pin 8 | I/O β User I/O pin (macrocell input/output) |
| Pin 9 | I/O β User I/O pin (macrocell input/output) |
| Pin 10 | I/O β User I/O pin (macrocell input/output) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (macrocell input/output) |
| Pin 13 | I/O β User I/O pin (macrocell input/output) |
| Pin 14 | I/O β User I/O pin (macrocell input/output) |
| Pin 15 | I/O β User I/O pin (macrocell input/output) |
| Pin 16 | I/O β User I/O pin (macrocell input/output) |
| Pin 17 | I/O β User I/O pin (macrocell input/output) |
| Pin 18 | I/O β User I/O pin (macrocell input/output) |
| Pin 19 | I/O β User I/O pin (macrocell input/output) |
| Pin 20 | I/O β User I/O pin (macrocell input/output) |
| Pin 21 | I/O β User I/O pin (macrocell input/output) |
| Pin 22 | VCC β 5.0 V supply voltage |
| Pin 23 | I/O β User I/O pin (macrocell input/output) |
| Pin 24 | I/O β User I/O pin (macrocell input/output) |
| Pin 25 | I/O β User I/O pin (macrocell input/output) |
| Pin 26 | I/O β User I/O pin (macrocell input/output) |
| Pin 27 | I/O β User I/O pin (macrocell input/output) |
| Pin 28 | I/O β User I/O pin (macrocell input/output) |
| Pin 29 | I/O β User I/O pin (macrocell input/output) |
| Pin 30 | I/O β User I/O pin (macrocell input/output) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin (macrocell input/output) |
| Pin 33 | I/O β User I/O pin (macrocell input/output) |
| Pin 34 | I/O β User I/O pin (macrocell input/output) |
| Pin 35 | I/O β User I/O pin (macrocell input/output) |
| Pin 36 | I/O β User I/O pin (macrocell input/output) |
| Pin 37 | I/O β User I/O pin (macrocell input/output) |
| Pin 38 | I/O β User I/O pin (macrocell input/output) |
| Pin 39 | I/O β User I/O pin (macrocell input/output) |
| Pin 40 | I/O β User I/O pin (macrocell input/output) |
| Pin 41 | I/O β User I/O pin (macrocell input/output) |
| Pin 42 | VCC β 5.0 V supply voltage |
| Pin 43 | I/O β User I/O pin (macrocell input/output) |
| Pin 44 | I/O β User I/O pin (macrocell input/output) |
| Pin 45 | I/O β User I/O pin (macrocell input/output) |
| Pin 46 | I/O β User I/O pin (macrocell input/output) |
| Pin 47 | I/O β User I/O pin (macrocell input/output) |
| Pin 48 | I/O β User I/O pin (macrocell input/output) |
| Pin 49 | I/O β User I/O pin (macrocell input/output) |
| Pin 50 | I/O β User I/O pin (macrocell input/output) |
| Pin 51 | I/O β User I/O pin (macrocell input/output) |
| Pin 52 | GND β Ground |
| Pin 53 | I/O β User I/O pin (macrocell input/output) |
| Pin 54 | I/O β User I/O pin (macrocell input/output) |
| Pin 55 | I/O β User I/O pin (macrocell input/output) |
| Pin 56 | I/O β User I/O pin (macrocell input/output) |
| Pin 57 | TDI β JTAG Test Data In |
| Pin 58 | TMS β JTAG Test Mode Select |
| Pin 59 | TCK β JTAG Test Clock |
| Pin 60 | TDO β JTAG Test Data Out |
| Pin 61 | I/O β User I/O pin (macrocell input/output) |
| Pin 62 | I/O β User I/O pin (macrocell input/output) |
| Pin 63 | I/O β User I/O pin (macrocell input/output) |
| Pin 64 | I/O β User I/O pin (macrocell input/output) |
| Pin 65 | I/O β User I/O pin (macrocell input/output) |
| Pin 66 | I/O β User I/O pin (macrocell input/output) |
| Pin 67 | I/O β User I/O pin (macrocell input/output) |
| Pin 68 | I/O β User I/O pin (macrocell input/output) |
| Pin 69 | I/O β User I/O pin (macrocell input/output) |
| Pin 70 | I/O β User I/O pin (macrocell input/output) |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β User I/O pin (macrocell input/output) |
| Pin 73 | I/O β User I/O pin (macrocell input/output) |
| Pin 74 | I/O β User I/O pin (macrocell input/output) |
| Pin 75 | I/O β User I/O pin (macrocell input/output) |
| Pin 76 | I/O β User I/O pin (macrocell input/output) |
| Pin 77 | I/O β User I/O pin (macrocell input/output) |
| Pin 78 | I/O β User I/O pin (macrocell input/output) |
| Pin 79 | I/O β User I/O pin (macrocell input/output) |
| Pin 80 | I/O β User I/O pin (macrocell input/output) |
| Pin 81 | I/O β User I/O pin (macrocell input/output) |
| Pin 82 | VCC β 5.0 V supply voltage |
| Pin 83 | I/O β User I/O pin (macrocell input/output) |
| Pin 84 | I/O β User I/O pin (macrocell input/output) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7096LC84-7 is suitable for 6 applications: Legacy 5V Bus Address Decoding, Industrial 5V Glue Logic Consolidation, Peripheral Interface Bridging, Asynchronous State Machine Controllers, VME/PCI Board Replacement Logic, Board-Level Reset and Power Sequencer.
Legacy 5V Bus Address Decoding
The EPM7096LC84-7's 96 macrocells and 7.5 ns tPD make it ideal for legacy 5V ISA/PCI bus address decoder and chip-select generation. The MAX 7000 architecture provides deterministic timing via the PIA interconnect, so address-to-CS propagation delay is guaranteed within 7.5 ns regardless of routing - critical when feeding fast peripherals or memory mapped peripherals on an 8 MHz or 16 MHz bus. Placed between the address bus and peripheral CS pins; the JTAG interface allows in-system reprogramming when the board layout is locked. Compared to a discrete 74LS/74F TTL decoder, the CPLD replaces 4-8 decoder/AND/OR packages with one IC, freeing board area for legacy 5V backplanes.
Recommended
Industrial 5V Glue Logic Consolidation
The EPM7096LC84-7 consolidates dozens of 74-series glue-logic gates into one CPLD on legacy industrial PLC and process-control boards. With 96 macrocells and 64 user I/Os, it can replace 5-15 discrete SSI/MSI packages (74LS00, 74LS138, 74LS244, 74LS374) while the 5V-tolerant I/Os match existing 5V backplanes directly. The EEPROM non-volatile configuration provides instant-on behavior at power-up - critical for industrial safety and deterministic boot, unlike FPGAs that require configuration ROM boot time. The 7.5 ns tPD accommodates timing budgets up to 133 MHz for high-speed encoder counters.
Recommended
Peripheral Interface Bridging
The EPM7096LC84-7 bridges incompatible peripheral interfaces (e.g., 8-bit microcontroller port to 16-bit ISA bus, or parallel port to serial UART expansion). The 64 user I/Os and 96 macrocells are sufficient to implement protocol converters, FIFOs, and handshaking logic in a single chip, while the 5V tolerance allows direct connection to legacy 5V peripheral ICs without level shifters. The JTAG ISP enables field reprogramming for protocol upgrades. The 7.5 ns tPD keeps handshaking latency below 1 bus cycle at 33 MHz, making the part suitable for real-time peripheral emulation in industrial and telecom systems.
Recommended
Asynchronous State Machine Controllers
The EPM7096LC84-7 implements asynchronous state machines for reset sequencing, power-good generation, and watchdog logic in embedded systems. Each of the 96 macrocells includes a programmable flip-flop with individual clear, preset, clock, and clock-enable controls - exactly the primitives needed for Mealy/Moore state machines. The MAX 7000 PIA routing is non-blocking for asynchronous paths, so state transitions remain glitch-free under all input combinations. The 7.5 ns tPD enables sub-microsecond reset propagation chains for multi-rail processor sequencing. The 5V tolerance and PLCC-84 footprint also suit legacy telecom shelf controllers.
Recommended
VME/PCI Board Replacement Logic
The EPM7096LC84-7 is widely used on legacy VMEbus and PCI add-in cards for bus arbitration, interrupt steering, and IDSEL decoding. The 5V-tolerant I/Os are essential for direct connection to VMEbus drivers and receivers (DS0026, 74LS245), eliminating level-shift logic. With 7.5 ns tPD, the CPLD meets VME DTB arbitration timing on 16-bit and 32-bit transfers without wait states. The 64 user I/Os also accommodate full VME interrupt acknowledge (IACK) Daisy-Chain driver implementations. The 84-pin PLCC footprint has been an industry-standard package for VME/PCI board designers for two decades.
Recommended
Board-Level Reset and Power Sequencer
The EPM7096LC84-7 functions as a board-level reset and power-sequencing controller in multi-rail systems, generating sequenced reset pulses to FPGAs, ASICs, and microcontrollers with precise timing. With 96 macrocells, the part can implement up to 8 sequenced rails with independent delay programming, brownout detection, and watchdog timer logic. The 5V I/O tolerance allows direct connection to supervisor ICs and power-good signals from DC-DC converters. The 7.5 ns tPD provides fast response to brownout events, while the JTAG ISP allows last-minute delay adjustment without board rework. The PLCC-84 package is favored for through-hole rework on legacy boards.
Recommended
Recommended Products Summary
Engineering reference data for EPM7096LC84-7 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7096LC84-10 | EPM7096LC84-15 | EPM7096LC68-7 | EPM7096LC68-15 | EPM7128ELC84-7 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Package | PLCC-84 | PLCC-84 - same | PLCC-84 - same | PLCC-68 - smaller footprint | PLCC-68 - smaller footprint | PLCC-84 - same |
| Macrocells | 96 | 96 | 96 | 96 | 96 | 128 (+33%) |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 10 ns | 15 ns | 7.5 ns | 15 ns | 7.5 ns |
| User I/O Pins | 64 | 64 | 64 | 52 (fewer due to 68-pin PLCC) | 52 (fewer due to 68-pin PLCC) | 68 |
| Logic Array Blocks (LABs) | 4 | 4 | 4 | 4 | 4 | 8 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| JTAG ISP | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) | Yes (IEEE 1149.1) |
| Lifecycle Status | Obsolete (PCN/PDN issued) | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Fastest speed grade in the 96-macrocell MAX 7000 84-pin PLCC family (vs EPM7096LC84-10)
- More user I/Os than the 68-pin PLCC variants (vs EPM7096LC68-7)
- Lower macrocell density but same MAX 7000 architecture as the 128-macrocell upgrade (vs EPM7128ELC84-7)
Design Notes
The EPM7096LC84-7 requires a stable 5.0 V supply with decoupling placed within 5 mm of each VCC pin (pins 22, 42, 82) and each GND pin (11, 31, 52, 71). Use a 100 nF ceramic + 10 uF tantalum bulk capacitor combination per rail, plus 1 uF near the JTAG TCK pin to suppress switching noise. The LC family draws ICC in the low milliamp range during static operation but can spike to ~200 mA during JTAG programming - ensure the regulator has adequate transient response. Brownout below 4.5 V may cause configuration corruption; add a TL7705 supervisor IC to drive a global reset.
For the 84-pin PLCC package, use a PLCC-84 socket (e.g., 3M 8484-21B1 or Aries 84-PRS) when designing for field programming flexibility. The PLCC-84 footprint requires rectangular SMT pads approximately 1.27 mm wide on 1.27 mm pitch, with a center pad for socket alignment. Add a JTAG header (2x5 or 2x7 0.1" pitch) connected to TCK/TMS/TDI/TDO plus GND and VCC for in-system programming via Altera ByteBlaster or USB-Blaster. Keep JTAG trace lengths under 100 mm to avoid signal integrity issues at high TCK frequencies.
Do not confuse the EPM7096LC84-7 (LC commercial temp) with the EPM7096QE84 (industrial QPFG temp) - they have different operating temperature ranges. Do not apply 3.3 V to VCC - the LC family is 5.0 V only. Do not enable global clock/clear/preset pins as user I/O without first checking the Quartus MAX 7000 device pinout file; doing so may cause configuration errors. When migrating from EPM7064 (64 macrocells) to EPM7096 (96 macrocells), recompile the design - the LAB structure differs and pin assignments may need re-mapping. Always issue a full erase before reprogramming an EEPROM-based MAX 7000 device via JTAG to prevent cell overstress.
On legacy 5V buses with fast edges (>1 ns rise time), series-terminate the I/O outputs with 33 ohm resistors to dampen reflections on long traces. The MAX 7000 output drive strength is rated at 25 mA per pin, but simultaneous switching of 8+ outputs can cause ground bounce - distribute heavily-loaded outputs across all four LABs to avoid localized GND noise. For inputs driven by 5V TTL devices, no clamping is required because the MAX 7000 LC family is 5V-tolerant; however, do not apply voltages above VCC + 0.5 V or below GND - 0.5 V. Use the dedicated JTAG pins only for JTAG operations; assigning them as user I/O requires disabling JTAG permanently and is not recommended for production.
Compliance Information
Original Altera MAX 7000 family PLCC-84 package uses lead (Pb) in solder balls/terminations and is therefore not RoHS compliant per Intel's product environmental compliance data. REACH compliant per EU regulation. Not AEC-Q100 qualified (commercial temp only, LC suffix). Halogen-free per JEDEC JS709. Conflict-minerals compliant per Section 1502 of the Dodd-Frank Act. For RoHS-compliant equivalent, consider MAX V CPLDs in lead-free packages.
