EPM7096LC68-15 - MAX 7000 CPLD, 96 Macrocells, 15ns | Altera
MPN: EPM7096LC68-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.25 | $112.50 |
| 100 | $9.85 | $985.00 |
| 500 | $8.4 | $4,200.00 |
| 1,000 | $7.2 | $7,200.00 |
Drop-in alternatives for EPM7096LC68-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128SLC68-15
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SLC68-10
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SLC68-7
β Drop-Inπ Reference alternative (not in catalog)
EPM7096LC68-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Macrocells | 96 |
| Logic Array Blocks (LABs) | 4 |
| User I/O Pins | 52 |
| Propagation Delay (tPD) | 15 ns |
| Supply Voltage (VCCINT/VCCIO) | 4.75 V to 5.25 V (5 V nominal) |
| Programmable Technology | EEPROM (second-generation MAX architecture) |
| In-System Programming | Yes (IEEE 1149.1 JTAG) |
| Logic Gates (typical) | 1800 gates |
| Memory Bits | Non-volatile configuration, 100 erase/program cycles per macrocell |
| Package | PLCC-68 (LC68) |
| Mounting Type | Surface Mount (PLCC socket compatible) |
| Operating Temperature | 0C to +70C (commercial) |
| Lead-Free / RoHS | Compliant per Altera product page |
| Programming Tool Support | Altera MAX+PLUS II, Quartus II; ByteBlaster / ByteBlasterMV |
EPM7096LC68-15 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | I/O β User I/O pin (bank 1) |
| Pin 14 | TDI β JTAG Test Data In |
| Pin 15 | TMS β JTAG Test Mode Select |
| Pin 16 | TCK β JTAG Test Clock |
| Pin 17 | I/O β User I/O pin (bank 1) |
| Pin 18 | I/O β User I/O pin (bank 1) |
| Pin 19 | I/O β User I/O pin (bank 1) |
| Pin 20 | I/O β User I/O pin (bank 1) |
| Pin 21 | VCC β 5V supply (bank 1) |
| Pin 22 | I/O β User I/O pin (bank 1) |
| Pin 23 | I/O β User I/O pin (bank 1) |
| Pin 24 | I/O β User I/O pin (bank 1) |
| Pin 25 | I/O β User I/O pin (bank 1) |
| Pin 26 | I/O β User I/O pin (bank 1) |
| Pin 27 | I/O β User I/O pin (bank 1) |
| Pin 28 | I/O β User I/O pin (bank 1) |
| Pin 29 | I/O β User I/O pin (bank 1) |
| Pin 30 | I/O β User I/O pin (bank 1) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin (bank 1) |
| Pin 33 | I/O β User I/O pin (bank 1) |
| Pin 34 | I/O β User I/O pin (bank 1) |
| Pin 35 | I/O β User I/O pin (bank 1) |
| Pin 36 | I/O β User I/O pin (bank 1) |
| Pin 37 | I/O β User I/O pin (bank 1) |
| Pin 38 | I/O β User I/O pin (bank 1) |
| Pin 39 | I/O β User I/O pin (bank 1) |
| Pin 40 | I/O β User I/O pin (bank 1) |
| Pin 41 | VCC β 5V supply (bank 1) |
| Pin 42 | I/O β User I/O pin (bank 1) |
| Pin 43 | I/O β User I/O pin (bank 1) |
| Pin 44 | I/O β User I/O pin (bank 1) |
| Pin 45 | I/O β User I/O pin (bank 1) |
| Pin 46 | I/O β User I/O pin (bank 1) |
| Pin 47 | I/O β User I/O pin (bank 1) |
| Pin 48 | I/O β User I/O pin (bank 1) |
| Pin 49 | I/O β User I/O pin (bank 1) |
| Pin 50 | I/O β User I/O pin (bank 1) |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O pin (bank 1) |
| Pin 53 | I/O β User I/O pin (bank 1) |
| Pin 54 | I/O β User I/O pin (bank 1) |
| Pin 55 | I/O β User I/O pin (bank 1) |
| Pin 56 | I/O β User I/O pin (bank 1) |
| Pin 57 | I/O β User I/O pin (bank 1) |
| Pin 58 | I/O β User I/O pin (bank 1) |
| Pin 59 | I/O β User I/O pin (bank 1) |
| Pin 60 | I/O β User I/O pin (bank 1) |
| Pin 61 | VCC β 5V supply (bank 1) |
| Pin 62 | I/O β User I/O pin (bank 1) |
| Pin 63 | I/O β User I/O pin (bank 1) |
| Pin 64 | I/O β User I/O pin (bank 1) |
| Pin 65 | I/O β User I/O pin (bank 1) |
| Pin 66 | I/O β User I/O pin (bank 1) |
| Pin 67 | TDO β JTAG Test Data Out |
| Pin 68 | I/O β User I/O pin (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7096LC68-15 is suitable for 6 applications: Microprocessor Address Decoding, Bus Interface and Protocol Bridging, State Machine Controllers, TTL Glue Logic Replacement, Power-Up Sequencing Logic, Legacy Industrial Control and Test Equipment.
Microprocessor Address Decoding
The EPM7096LC68-15 fits address-decoding tasks because 96 macrocells easily map a full 24-bit address decode tree plus chip-select glue logic, and its 15 ns tPD is faster than most 5V microprocessors of its era. Placed between the processor and peripheral bus, it replaces a bank of 74LS138 / 74LS139 decoders with one PLCC-68 device. Its non-volatile EEPROM boots in a deterministic state, so chip selects are valid on the very first clock cycle without waiting for FPGA configuration. The 5V TTL-compatible I/O simplifies interface to legacy 8086, 68k, and 8051-style buses without level shifters.
Recommended
Bus Interface and Protocol Bridging
The EPM7096LC68-15 is widely used as a glue-logic bridge between mismatched bus standards (ISA, PCI, VME, parallel data ports) because 96 macrocells handle full 16-bit or 32-bit state machines and 52 I/O pins expose enough user signals for multi-bus fan-out. Its 15 ns propagation delay comfortably meets ISA and VME bus timing budgets. In-system JTAG programming lets field engineers re-flash the bridge logic without removing the card from the chassis. The 5V-tolerant I/O matches legacy peripheral ASICs without external buffers.
Recommended
State Machine Controllers
With 96 macrocells and deterministic 15 ns timing, the EPM7096LC68-15 implements multi-state Mealy and Moore controllers for industrial sequencing, vending machines, and instrument front panels. Each macrocell's flip-flop plus the AND/OR array maps cleanly onto standard one-hot or binary-encoded state diagrams. The deterministic tPD makes worst-case timing analyzable without statistical static timing analysis tooling. The non-volatile EEPROM boots to a known state on every power-up, which is critical for safety interlocks.
Recommended
TTL Glue Logic Replacement
Engineers replace banks of 74LS/74HC glue logic with a single EPM7096LC68-15 to consolidate scattered gates, reduce PCB area, and improve design revision flexibility. Up to 96 macrocells can absorb the equivalent of 30 to 50 SSI/MSI packages, with 52 user I/O pins exposed for signal fan-in and fan-out. JTAG programming lets engineers iterate the logic without board rework. The 5V supply directly replaces TTL rails without level translation.
Recommended
Power-Up Sequencing Logic
The EPM7096LC68-15 is a natural fit for power-up and power-down sequencing in multi-rail systems because its non-volatile EEPROM guarantees a deterministic output state from the very first clock cycle. Engineers encode the rail-enable order, fault detection, and reset pulse generation inside one PLCC-68 device. The 5V supply rails match typical housekeeping regulators in telecom and industrial chassis. The 15 ns delay is faster than any external power-good comparator it would replace.
Recommended
Legacy Industrial Control and Test Equipment
Industrial controllers, programmable logic controllers (PLCs), and ATE test equipment from the 1990s and 2000s used the EPM7096LC68-15 because of its 5V tolerance, 96-macrocell capacity, and PLCC-68 socket-friendly package. The device reliably implements encoder counters, quadrature decoders, and timing-pulse generators at 15 ns. Field-replaceable PLCC sockets make board swaps painless in 24/7 production environments. Replacement boards are still designed around this CPLD to avoid revalidating regulatory certifications.
Recommended
Recommended Products Summary
Engineering reference data for EPM7096LC68-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SLC68-15 | EPM7128SLC68-10 | EPM7128SLC68-7 |
|---|---|---|---|---|
| Package | PLCC-68 (LC68) | PLCC-68 (LC68) - same | PLCC-68 (LC68) - same | PLCC-68 (LC68) - same |
| Brand | Altera | Altera | Altera | Altera |
| Macrocells | 96 | 128 (+33%) | 128 (+33%) | 128 (+33%) |
| Propagation Delay (tPD) | 15 ns | 15 ns (same) | 10 ns (-33%) | 7 ns (-53%) |
| Logic Array Blocks | 4 LABs | 8 LABs | 8 LABs | 8 LABs |
| User I/O Pins | 52 | 52 (same) | 52 (same) | 52 (same) |
| Supply Voltage | 5.0 V (4.75-5.25 V) | 5.0 V (same) | 5.0 V (same) | 5.0 V (same) |
| In-System Programming | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Unit Price (qty 1, USD) | 12.50 | 14.00 | 16.50 | 20.00 |
Key Differentiators
- Drop-in upgrade path to higher-density MAX 7000 family (vs EPM7128SLC68-15)
- In-system JTAG programmability (vs EPM7064LC68 (smaller family member))
- Non-volatile EEPROM, deterministic boot (vs SRAM-based FPGAs (e.g. FLEX 10K series))
Design Notes
The EPM7096LC68-15 operates from a single 5.0 V (4.75 V to 5.25 V) supply. Estimated: with 52 I/Os toggling at moderate CMOS loading, the device draws roughly 50 to 150 mA dynamic plus EEPROM programming current during ISP. Decouple every VCC pin (1, 21, 41, 61 in PLCC-68) with a 0.1 uF ceramic cap placed within 5 mm of the pin, and add a single 10 uF bulk tantalum or ceramic capacitor near the package. JTAG ISP pulses can briefly raise Icc, so adequate bulk capacitance prevents the rail from sagging during programming.
The PLCC-68 footprint supports both surface-mount soldering and a through-hole PLCC socket, which is convenient for legacy industrial boards. Place the JTAG header (TCK, TMS, TDI, TDO plus optional TRST) within 100 mm of the device and route TDI/TDO with series 100 ohm termination to dampen ringing. Keep TCK and TMS away from clock edges on adjacent I/O banks; route them on an inner layer with ground reference to limit crosstalk.
Do not assume the EPM7096LC68-15 is 3.3V tolerant - all I/O banks operate at 5V TTL levels and exceeding 5.25 V will damage the EEPROM cells. Do not program the part with a 3.3V-only JTAG programmer; use Altera ByteBlasterMV or a 5V-tolerant download cable. When migrating a design from EPM7096LC68-15 to EPM7128SLC68-15 in the same socket, recompile the project in MAX+PLUS II or Quartus to regenerate the JEDEC file; the macrocell counts differ and the bitstream is not interchangeable.
Each macrocell output has a programmable slew rate (slow/fast); for switching frequencies above 33 MHz or for heavily loaded buses, select the slow slew-rate option to reduce ground bounce. Place 22 ohm to 33 ohm series resistors on high-edge-rate outputs driving long PCB traces or backplane connectors. The MAX 7000 internal interconnect is non-multiplexed and deterministic, so static timing analysis in Quartus yields the exact worst-case tCO and tSU values without statistical margins.
Compliance Information
RoHS compliant per Altera product page. Not AEC-Q100 qualified - this is a commercial-grade part intended for industrial and consumer environments. Halogen-free status not explicitly stated in the verified data.
