EPM7128AETC100-7N vs EPM7128AETI100-7 Comparison
Detailed side-by-side comparison of EPM7128AETC100-7N by Altera and EPM7128AETI100-7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128AETI100-7 - MAX 7000A CPLD, 128 Macrocells, 100-TQFP | Altera
EPM7128AETI100-7 ObsoleteSpecification Comparison
| Parameter | EPM7128AETC100-7N | EPM7128AETI100-7 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 4 | — |
| User I/Os | 84 | 84 |
| Propagation Delay (tpd) | 7.5 ns | — |
| Counter Frequency (max) | 129.9 MHz | — |
| Internal Frequency (max) | 250 MHz | — |
| Core Supply Voltage | 3.3 V | — |
| Logic Family | CMOS | — |
| Pin Count | 100 | — |
| Package | 100-TQFP | 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 C to +70 C (Commercial) | -40 C to +85 C (Industrial) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm RoHS for non-N suffix] |
| Process Technology | 0.30 µm EEPROM CMOS | — |
| Macrocells | — | 128 |
| Logic Blocks (LABs) | — | 8 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Maximum Counter Frequency | — | 129.9 MHz |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| I/O Bank Supply (VCCIO) | — | 2.5 V / 3.3 V / 5 V (MultiVolt) |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Global Clock Inputs | — | 4 dedicated |
| Lead-Free Version (MPN Suffix) | — | -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) |