EPM7128AETC144-7N vs EPM7128ATC144-10 Comparison
Detailed side-by-side comparison of EPM7128AETC144-7N by Altera and EPM7128ATC144-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128AETC144-7N
EPM7128AETC144-7N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel / Altera
EPM7128AETC144-7N β ActiveAltera
EPM7128ATC144-10
EPM7128ATC144-10 - 128-Macrocell MAX 7000A CPLD | Intel / Altera
EPM7128ATC144-10 ObsoleteSpecification Comparison
| Parameter | EPM7128AETC144-7N | EPM7128ATC144-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $39.82 | $9.10 |
| Family | MAX 7000A | β |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Logic Gates | 2500 (2.5K gates) | β |
| Macro Cells | 128 | β |
| User I/Os | 36 (in 144-pin TQFP) | β |
| Maximum Operating Frequency | 129.9 MHz | β |
| Pin-to-Pin Delay | 7.5 ns | β |
| Propagation Delay (tpd) | 7.5 ns | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| Process Technology | CMOS, EEPROM-based | β |
| Programmability | In-System Programmable (ISP) via JTAG | β |
| Boundary-Scan Test | IEEE Std 1149.1 (JTAG) | β |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Package | 144-pin TQFP | β |
| Mounting Type | Surface Mount | Surface Mount |
| Pin-Compatible With | MAX 7000S 5.0V family (144-pin TQFP) | β |
| RoHS Status | Compliant | unknown (legacy Altera device) |
| Lead-Free | Yes | β |
| Manufacturer | β | Altera (now Intel) |
| Series | β | MAX 7000A |
| Programmable Type | β | EE PLD (EEPROM-based, in-system programmable) |
| Macrocells | β | 128 |
| Logic Array Blocks | β | 4 |
| User I/O Pins | β | 68 |
| Propagation Delay (tPD) | β | 10 ns |
| Maximum Counter Frequency | β | 98 MHz |
| Supply Voltage - Internal (VCCINT) | β | 3.0 V to 3.6 V |
| I/O Voltage Levels | β | 5.0 V / 3.3 V / 2.5 V compatible (MultiVolt I/O) |
| In-System Programmability | β | Yes (IEEE Std 1149.1 JTAG) |
| Package / Case | β | 144-TQFP (20 x 20 mm) |
| Architecture | β | Multiple Array Matrix (MAX), 2nd generation |