EPM7128AETC144-7N vs EPM7128ATC144-10 Comparación
Comparación detallada lado a lado de EPM7128AETC144-7N por Altera y EPM7128ATC144-10 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EPM7128AETC144-7N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel / Altera
EPM7128AETC144-7N ✓ ActivoComparación de especificaciones
| Parámetro | EPM7128AETC144-7N | EPM7128ATC144-10 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $39,82 | $9,10 |
| Family | MAX 7000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Logic Gates | 2500 (2.5K gates) | — |
| Macro Cells | 128 | — |
| User I/Os | 36 (in 144-pin TQFP) | — |
| Maximum Operating Frequency | 129.9 MHz | — |
| Pin-to-Pin Delay | 7.5 ns | — |
| Propagation Delay (tpd) | 7.5 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Process Technology | CMOS, EEPROM-based | — |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| Boundary-Scan Test | IEEE Std 1149.1 (JTAG) | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Encapsulado | 144-pin TQFP | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Pin-Compatible With | MAX 7000S 5.0V family (144-pin TQFP) | — |
| Estado RoHS | Compliant | unknown (legacy Altera device) |
| Lead-Free | Yes | — |
| Manufacturer | — | Altera (now Intel) |
| Series | — | MAX 7000A |
| Programmable Type | — | EE PLD (EEPROM-based, in-system programmable) |
| Macrocells | — | 128 |
| Logic Array Blocks | — | 4 |
| User I/O Pins | — | 68 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 98 MHz |
| Supply Voltage - Internal (VCCINT) | — | 3.0 V to 3.6 V |
| I/O Voltage Levels | — | 5.0 V / 3.3 V / 2.5 V compatible (MultiVolt I/O) |
| In-System Programmability | — | Yes (IEEE Std 1149.1 JTAG) |
| Encapsulado / Carcasa | — | 144-TQFP (20 x 20 mm) |
| Architecture | — | Multiple Array Matrix (MAX), 2nd generation |