EPM7128AETC144-7N vs EPM7128ATC144-10 对比

详细并排对比 EPM7128AETC144-7N 出自 Altera 和 EPM7128ATC144-10 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM7128AETC144-7N EPM7128ATC144-10
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $39.82 $9.10
Family MAX 7000A —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Logic Gates 2500 (2.5K gates) —
Macro Cells 128 —
User I/Os 36 (in 144-pin TQFP) —
Maximum Operating Frequency 129.9 MHz —
Pin-to-Pin Delay 7.5 ns —
Propagation Delay (tpd) 7.5 ns —
Supply Voltage (VCCINT) 3.3 V —
Process Technology CMOS, EEPROM-based —
Programmability In-System Programmable (ISP) via JTAG —
Boundary-Scan Test IEEE Std 1149.1 (JTAG) —
工作温度 0C to +70C (commercial) 0C to +70C (commercial)
封装 144-pin TQFP —
安装类型 Surface Mount Surface Mount
Pin-Compatible With MAX 7000S 5.0V family (144-pin TQFP) —
RoHS 状态 Compliant unknown (legacy Altera device)
Lead-Free Yes —
Manufacturer — Altera (now Intel)
Series — MAX 7000A
Programmable Type — EE PLD (EEPROM-based, in-system programmable)
Macrocells — 128
Logic Array Blocks — 4
User I/O Pins — 68
Propagation Delay (tPD) — 10 ns
Maximum Counter Frequency — 98 MHz
Supply Voltage - Internal (VCCINT) — 3.0 V to 3.6 V
I/O Voltage Levels — 5.0 V / 3.3 V / 2.5 V compatible (MultiVolt I/O)
In-System Programmability — Yes (IEEE Std 1149.1 JTAG)
封装 / 外壳 — 144-TQFP (20 x 20 mm)
Architecture — Multiple Array Matrix (MAX), 2nd generation

数据手册与资源

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