EPM7128ATC144-10 - 128-Macrocell MAX 7000A CPLD | Intel / Altera
MPN: EPM7128ATC144-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $13.2 | $132.00 |
| 100 | $11.85 | $1,185.00 |
| 500 | $10.4 | $5,200.00 |
| 1,000 | $9.1 | $9,100.00 |
Drop-in alternatives for EPM7128ATC144-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128AETC144-10
β Drop-Inβ In Stock
$21.7 / Unit
View Datasheet βEPM7128AETC144-7N
β Drop-Inβ In Stock
$39.82 / Unit
View Datasheet βEPM7128AETC144-7
β Drop-Inβ In Stock
$16.4 / Unit
View Datasheet βEPM7128AETI144-10N
β Drop-Inβ In Stock
$23.1 / Unit
View Datasheet βEPM7128AETC144-10N
β Drop-Inπ Reference alternative (not in catalog)
EPM7128ATC144-10 Maximum Ratings & Electrical Characteristics
| Manufacturer | Altera (now Intel) |
| Series | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Programmable Type | EE PLD (EEPROM-based, in-system programmable) |
| Macrocells | 128 |
| Logic Array Blocks | 4 |
| User I/O Pins | 68 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Counter Frequency | 98 MHz |
| Supply Voltage - Internal (VCCINT) | 3.0 V to 3.6 V |
| I/O Voltage Levels | 5.0 V / 3.3 V / 2.5 V compatible (MultiVolt I/O) |
| In-System Programmability | Yes (IEEE Std 1149.1 JTAG) |
| Operating Temperature | 0C to +70C (commercial) |
| Package / Case | 144-TQFP (20 x 20 mm) |
| Mounting Type | Surface Mount |
| Architecture | Multiple Array Matrix (MAX), 2nd generation |
| RoHS Status | unknown (legacy Altera device) |
EPM7128ATC144-10 Pin Configuration
| Pin 1 | I/O β User I/O (Bank 1) |
| Pin 2 | I/O β User I/O (Bank 1) |
| Pin 3 | I/O β User I/O (Bank 1) |
| Pin 4 | I/O β User I/O (Bank 1) |
| Pin 5 | I/O β User I/O (Bank 1) |
| Pin 6 | I/O β User I/O (Bank 1) |
| Pin 7 | I/O β User I/O (Bank 1) |
| Pin 8 | I/O β User I/O (Bank 1) |
| Pin 9 | I/O β User I/O (Bank 1) |
| Pin 10 | GND β Ground |
| Pin 11 | I/O β User I/O (Bank 1) |
| Pin 12 | I/O β User I/O (Bank 1) |
| Pin 13 | I/O β User I/O (Bank 1) |
| Pin 14 | I/O β User I/O (Bank 1) |
| Pin 15 | I/O β User I/O (Bank 1) |
| Pin 16 | I/O β User I/O (Bank 1) |
| Pin 17 | I/O β User I/O (Bank 1) |
| Pin 18 | I/O β User I/O (Bank 1) |
| Pin 19 | GND β Ground |
| Pin 20 | I/O β User I/O (Bank 2) |
| Pin 21 | I/O β User I/O (Bank 2) |
| Pin 22 | I/O β User I/O (Bank 2) |
| Pin 23 | I/O β User I/O (Bank 2) |
| Pin 24 | I/O β User I/O (Bank 2) |
| Pin 25 | I/O β User I/O (Bank 2) |
| Pin 26 | I/O β User I/O (Bank 2) |
| Pin 27 | I/O β User I/O (Bank 2) |
| Pin 28 | I/O β User I/O (Bank 2) |
| Pin 29 | GND β Ground |
| Pin 30 | I/O β User I/O (Bank 2) |
| Pin 31 | I/O β User I/O (Bank 2) |
| Pin 32 | I/O β User I/O (Bank 2) |
| Pin 33 | I/O β User I/O (Bank 2) |
| Pin 34 | I/O β User I/O (Bank 2) |
| Pin 35 | I/O β User I/O (Bank 2) |
| Pin 36 | GND β Ground |
| Pin 37 | I/O β User I/O (Bank 3) |
| Pin 38 | I/O β User I/O (Bank 3) |
| Pin 39 | I/O β User I/O (Bank 3) |
| Pin 40 | I/O β User I/O (Bank 3) |
| Pin 41 | I/O β User I/O (Bank 3) |
| Pin 42 | I/O β User I/O (Bank 3) |
| Pin 43 | I/O β User I/O (Bank 3) |
| Pin 44 | I/O β User I/O (Bank 3) |
| Pin 45 | I/O β User I/O (Bank 3) |
| Pin 46 | GND β Ground |
| Pin 47 | I/O β User I/O (Bank 3) |
| Pin 48 | I/O β User I/O (Bank 3) |
| Pin 49 | I/O β User I/O (Bank 3) |
| Pin 50 | I/O β User I/O (Bank 3) |
| Pin 51 | I/O β User I/O (Bank 3) |
| Pin 52 | I/O β User I/O (Bank 3) |
| Pin 53 | I/O β User I/O (Bank 3) |
| Pin 54 | I/O β User I/O (Bank 3) |
| Pin 55 | GND β Ground |
| Pin 56 | I/O β User I/O (Bank 4) |
| Pin 57 | I/O β User I/O (Bank 4) |
| Pin 58 | I/O β User I/O (Bank 4) |
| Pin 59 | I/O β User I/O (Bank 4) |
| Pin 60 | I/O β User I/O (Bank 4) |
| Pin 61 | I/O β User I/O (Bank 4) |
| Pin 62 | I/O β User I/O (Bank 4) |
| Pin 63 | I/O β User I/O (Bank 4) |
| Pin 64 | I/O β User I/O (Bank 4) |
| Pin 65 | I/O β User I/O (Bank 4) |
| Pin 66 | GND β Ground |
| Pin 67 | I/O β User I/O (Bank 4) |
| Pin 68 | I/O β User I/O (Bank 4) |
| Pin 69 | I/O β User I/O (Bank 4) |
| Pin 70 | I/O β User I/O (Bank 4) |
| Pin 71 | I/O β User I/O (Bank 4) |
| Pin 72 | I/O β User I/O (Bank 4) |
| Pin 73 | TDI β JTAG Test Data In |
| Pin 74 | TMS β JTAG Test Mode Select |
| Pin 75 | TCK β JTAG Test Clock |
| Pin 76 | VCC β VCCINT (3.3 V core supply) |
| Pin 77 | VCC β VCCINT (3.3 V core supply) |
| Pin 78 | VCCIO β I/O supply Bank 1 |
| Pin 79 | VCCIO β I/O supply Bank 2 |
| Pin 80 | GND β Ground |
| Pin 81 | TDO β JTAG Test Data Out |
| Pin 82 | GCLK1 β Global Clock 1 |
| Pin 83 | GCLRn β Global Clear |
| Pin 84 | OE1 β Output Enable 1 |
| Pin 85 | OE2 β Output Enable 2 |
| Pin 86 | GND β Ground |
| Pin 87 | I/O β User I/O (Bank 1) |
| Pin 88 | I/O β User I/O (Bank 1) |
| Pin 89 | I/O β User I/O (Bank 1) |
| Pin 90 | I/O β User I/O (Bank 1) |
| Pin 91 | I/O β User I/O (Bank 1) |
| Pin 92 | I/O β User I/O (Bank 1) |
| Pin 93 | I/O β User I/O (Bank 1) |
| Pin 94 | I/O β User I/O (Bank 1) |
| Pin 95 | I/O β User I/O (Bank 1) |
| Pin 96 | I/O β User I/O (Bank 1) |
| Pin 97 | GND β Ground |
| Pin 98 | I/O β User I/O (Bank 1) |
| Pin 99 | I/O β User I/O (Bank 1) |
| Pin 100 | I/O β User I/O (Bank 1) |
| Pin 101 | I/O β User I/O (Bank 1) |
| Pin 102 | I/O β User I/O (Bank 1) |
| Pin 103 | I/O β User I/O (Bank 1) |
| Pin 104 | I/O β User I/O (Bank 1) |
| Pin 105 | I/O β User I/O (Bank 1) |
| Pin 106 | I/O β User I/O (Bank 1) |
| Pin 107 | GND β Ground |
| Pin 108 | I/O β User I/O (Bank 1) |
| Pin 109 | I/O β User I/O (Bank 1) |
| Pin 110 | I/O β User I/O (Bank 1) |
| Pin 111 | I/O β User I/O (Bank 1) |
| Pin 112 | I/O β User I/O (Bank 1) |
| Pin 113 | I/O β User I/O (Bank 1) |
| Pin 114 | I/O β User I/O (Bank 1) |
| Pin 115 | OE3 β Output Enable 3 |
| Pin 116 | OE4 β Output Enable 4 |
| Pin 117 | VCC β VCCINT (3.3 V core supply) |
| Pin 118 | VCC β VCCINT (3.3 V core supply) |
| Pin 119 | VCCIO β I/O supply Bank 3 |
| Pin 120 | VCCIO β I/O supply Bank 4 |
| Pin 121 | GND β Ground |
| Pin 122 | NC β Not connected |
| Pin 123 | NC β Not connected |
| Pin 124 | NC β Not connected |
| Pin 125 | NC β Not connected |
| Pin 126 | NC β Not connected |
| Pin 127 | NC β Not connected |
| Pin 128 | I/O β User I/O (Bank 2) |
| Pin 129 | I/O β User I/O (Bank 2) |
| Pin 130 | I/O β User I/O (Bank 2) |
| Pin 131 | I/O β User I/O (Bank 2) |
| Pin 132 | I/O β User I/O (Bank 2) |
| Pin 133 | I/O β User I/O (Bank 2) |
| Pin 134 | I/O β User I/O (Bank 2) |
| Pin 135 | I/O β User I/O (Bank 2) |
| Pin 136 | I/O β User I/O (Bank 2) |
| Pin 137 | GND β Ground |
| Pin 138 | I/O β User I/O (Bank 2) |
| Pin 139 | I/O β User I/O (Bank 2) |
| Pin 140 | I/O β User I/O (Bank 2) |
| Pin 141 | I/O β User I/O (Bank 2) |
| Pin 142 | I/O β User I/O (Bank 2) |
| Pin 143 | I/O β User I/O (Bank 2) |
| Pin 144 | GND β Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128ATC144-10 is suitable for 6 applications: PCI-to-ISA Bus Bridge Glue Logic, Address Decoding & Chip-Select Generation, Peripheral I/O Expansion & Wake-Up Logic, LED Display & Multiplexed Scanner, Legacy TTL/CMOS Glue Logic Replacement, State Machine & Sequencer Implementation.
PCI-to-ISA Bus Bridge Glue Logic
The EPM7128ATC144-10 is widely deployed as 5V/3.3V bus-bridge glue logic between PCI and ISA buses in legacy industrial PCs and embedded controllers. Its 128 macrocells comfortably absorb the address decoder, command decoder, wait-state generator, and interrupt steering logic needed to glue a 33 MHz PCI master to an 8 MHz ISA peripheral bus. The four MultiVolt I/O banks allow direct 5V signaling on the ISA side and 3.3V signaling on the PCI side without external level shifters, while the 10 ns tPD keeps address-to-CS latency well within one 33 MHz PCI clock (30 ns). Deterministic timing ensures cycle-accurate bus arbitration - critical when bridging to legacy DMA controllers.
Recommended
Address Decoding & Chip-Select Generation
The EPM7128ATC144-10 excels at generating chip-select (CS) and address-decoder outputs for microprocessors that lack enough native decoded outputs. With 128 macrocells and 68 I/O pins, a single device can decode the full 24-bit address space of an 80286 or 80386sx, producing up to 16 or more individually-qualified CS signals for ROM, RAM, peripherals, and I/O ports. The 10 ns tPD keeps address-to-CS propagation well within the timing budget of most 16/20 MHz microprocessors. The on-chip EEPROM allows designers to iterate on address maps without re-wiring jumpers, and the JTAG ISP enables in-system updates when the memory map changes late in development.
Recommended
Peripheral I/O Expansion & Wake-Up Logic
In battery-powered industrial controllers, the EPM7128ATC144-10 serves as an ultra-low-power I/O expander and wake-up logic block. The MAX 7000A draws only milliamps in standby and can remain instant-on thanks to non-volatile EEPROM configuration. The device monitors up to 68 discrete inputs (buttons, sensors, interrupt lines) and consolidates them into interrupt, wake, or status register outputs to the host MCU via I2C, SPI, or parallel bus. The MultiVolt I/O lets a 3.3V MCU talk to 5V sensors directly, eliminating level-translator ICs.
Recommended
LED Display & Multiplexed Scanner
The EPM7128ATC144-10 is a strong fit for LED display drivers, seven-segment multiplexers, and dot-matrix scanners used in industrial HMIs and digital signage. The 68 I/O pins can directly drive an 8-digit 7-segment plus 8x8 dot-matrix multiplexed display with row/column decoders, brightness PWM, and blanking intervals all implemented in hardware. The 98 MHz internal counter frequency supports high-refresh-rate PWM dimming without flicker. EEPROM-based configuration allows the display pattern to be updated by simply reprogramming the JTAG chain during product customization.
Recommended
Legacy TTL/CMOS Glue Logic Replacement
A common modernization use case for the EPM7128ATC144-10 is replacing dozens of discrete 74LS/74HC/74F series TTL gates, latches, and decoders with a single CPLD. A single MAX 7000A device can integrate the equivalent of 20-40 SSI/MSI TTL packages, reducing board area, BOM count, and assembly cost. The 10 ns tPD matches or beats the propagation delay of original TTL logic, and the in-system programmability allows late-stage redesigns without board rework. Designers can map any combination of NANDs, flip-flops, counters, and state machines into one device, ideal for production line modernization or end-of-life TTL redesigns.
Recommended
State Machine & Sequencer Implementation
The EPM7128ATC144-10 is well suited to implementing complex state machines, sequencers, and protocol controllers in industrial automation equipment. Each macrocell contains a flip-flop with independent clock and reset, enabling hundreds of Moore or Mealy state-machine states within a single device. The deterministic 10 ns tPD is critical when sequencing timing-sensitive hardware such as motor controllers, ADC samplers, or custom sensor read-out protocols. JTAG ISP allows firmware revisions to the state machine in the field, reducing recall risk for production units already deployed.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128ATC144-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128AETC144-10 | EPM7128AETC144-7N | EPM7128AETC144-7 | EPM7128AETI144-10N | EPM7128AETC144-10N |
|---|---|---|---|---|---|---|
| Package | 144-TQFP (20x20 mm) | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same | 144-TQFP (20x20 mm) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/O Pins | 68 | 68 | 68 | 68 | 68 | 68 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 7.5 ns | 7.5 ns | 10 ns | 10 ns |
| Max Counter Frequency | 98 MHz | 98 MHz | 125.5 MHz | 125.5 MHz | 98 MHz | 98 MHz |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Core Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Lead-Free (Pb-Free) | unknown | unknown | Yes (N suffix) | No | Yes (N suffix) | Yes (N suffix) |
| Series | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A |
Key Differentiators
- Commercial-grade 0C to +70C operating temperature (vs EPM7128AETC144-10)
- 10 ns pin-to-pin propagation delay (vs EPM7128AETC144-7N)
- 68 user I/O pins - higher density than 100-pin MAX 7000A siblings (vs EPM7128ATC100-10)
Design Notes
Estimated: at typical 3.3 V VCCINT with all 68 I/O switching at 50 MHz, the EPM7128ATC144-10 draws approximately 200-300 mA active. Provide a minimum of one 0.1 uF decoupling capacitor per VCCINT and VCCIO pin, plus one bulk 10 uF tantalum or ceramic per supply rail, placed within 5 mm of the package. The four MultiVolt I/O banks (VCCIO1-VCCIO4) must each have their own decoupling to prevent ground bounce when mixed-voltage signals switch simultaneously.
Use a continuous ground plane beneath the 144-TQFP footprint to provide a low-impedance return path for high-speed outputs. Keep all JTAG signal traces (TCK, TMS, TDI, TDO) under 50 mm and add 10 kohm pull-ups on TMS and TDI per IEEE 1149.1 recommendations. The four output-enable pins (OE1-OE4) should be tied to logic-high via 4.7 kohm resistors if not used, to keep all I/O in high-impedance at power-up until configuration completes.
Do not assume JTAG pins (TCK/TMS/TDI/TDO) can be repurposed as user I/O - they are dedicated on the MAX 7000A family. Ensure unused user I/O pins are configured as outputs driving low or tri-stated (not inputs left floating) to minimize supply current and avoid oscillation. The GCLRn pin is a global clear and should be tied to VCCIO through a 4.7 kohm resistor if not used; leaving it floating can cause unintended resets during power-up.
Compliance Information
Legacy Altera device with obsolete lifecycle status. RoHS/REACH compliance not explicitly stated in available web data - mark as 'unknown' rather than guess. The 'N' suffix on later variants (e.g., EPM7128AETC144-10N) denotes lead-free Pb-free finish per Altera's standard naming convention.
