EPM7128AETI100-7 vs EPM7128AET1100-7 Comparison

Detailed side-by-side comparison of EPM7128AETI100-7 by Altera and EPM7128AET1100-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM7128AET1100-7 EPM7128AET1100-7 - 128-Macrocell MAX 7000A CPLD | Intel

EPM7128AET1100-7 - 128-Macrocell MAX 7000A CPLD | Intel

EPM7128AET1100-7 ⚠ Last Time Buy

Specification Comparison

Parameter EPM7128AETI100-7 EPM7128AET1100-7
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Last Time Buy
Family MAX 7000A MAX 7000A (MAX 7000AE)
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 128 128
Usable Gates 2,500 2,500
User I/Os 84 —
Logic Blocks (LABs) 8 —
Pin-to-Pin Delay (tPD) 7.5 ns —
Maximum Counter Frequency 129.9 MHz —
Supply Voltage - Core (VCCINT) 3.3 V —
I/O Bank Supply (VCCIO) 2.5 V / 3.3 V / 5 V (MultiVolt) —
Configuration Memory EEPROM (non-volatile, in-system programmable) EEPROM (non-volatile, instant-on)
JTAG Support Yes (IEEE 1149.1 boundary-scan) —
Global Clock Inputs 4 dedicated —
Package 100-pin TQFP (1.0 mm pitch, 14 x 14 mm) TQFP-100
Operating Temperature -40 C to +85 C (Industrial) -40C to +85C (industrial)
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: confirm RoHS for non-N suffix] ROHS3 Compliant
Lead-Free Version (MPN Suffix) -N suffix denotes lead-free (e.g., EPM7128AETI100-7N) —
User I/O Pins — 84
Logic Elements / LABs — [DATA_NEEDED: LAB count for 7128A]
Speed Grade — -7 (5 ns pin-to-pin)
Supply Voltage VCC — 5.0 V (typical)
I/O Voltage Tolerance — 3.3 V / 5.0 V
Programming Interface — IEEE 1149.1 JTAG / ByteBlaster
MSL Level — 3 (168 hours, per JEDEC J-STD-020)
Lead-Free — Yes
Process Technology — CMOS, EEPROM-based

Datasheets & Resources

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